METHOD AND SYSTEM FOR IMPROVING PCI-E L1 ASPM EXIT LATENCY

• US 20090100280A1
• Filed: 10/11/2007
• Published: 04/16/2009
• Est. Priority Date: 10/11/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lindsay, Steven B.
• Granted Patent: US 9,146,892 B2
• Time in Patent Office: Days
• US Class Current: 713/321
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The disclosed systems and methods relate to improving PCI Express (PCI-E) L1 Active State Power Management (ASPM) exit latency by speculatively initiating early L1 exit based on a network stimulus. Aspects of the present invention may enable a higher level of performance and responsiveness while supporting the benefits of ASPM. Aspects of the present invention may minimize operational cost by reducing latency in processes that utilize a PCI-E interface. Aspects of the present invention may be embodied in a Network Interface Controller (NIC) or any other device with a PCI-E interface that supports ASPM.

Claims

1. A method for improving latency during active state power management, wherein the method comprises:

entering a low power PCI-E state;

anticipating a transaction that would require a full power PCI-E state; and

transitioning to the full power PCI-E state based on the anticipated transaction.

2. The method in claim 1, wherein anticipating the transaction comprises scheduling an event, wherein the event is initiated when a timer expires.

3. The method in claim 2, wherein the event comprises a status update.

4. The method in claim 2, wherein the event comprises an interrupt generation.

5. The method in claim 2, wherein the event comprises a transfer of statistics to a host.

6. The method in claim 1, wherein transitioning to the full power state occurs after a delay.

7. The method in claim 6, wherein the delay is based on time.

8. The method in claim 1, wherein anticipating the transaction comprises:

receiving a packet; and

verifying an address associated with the packet.

9. The method in claim 8, wherein transitioning to the full power PCI-E state occurs after a delay.

10. The method in claim 9, wherein the delay is based on time.

11. The method in claim 9, wherein the delay is based on an amount of data received.

12. The method in claim 11, wherein the delay is based on the amount of data receive relative to the length of the packet.

13. The method in claim 8, wherein the method comprises checking the packet for error after transitioning to the full power PCI-E state and then initiating a transition back to the low power (11) state after an inactivity timer expires.

14. A method for reducing transitions during active state power management, wherein the method comprises:

anticipating a DMA transaction; and

resetting an inactivity timer based on the anticipated DMA transaction.

15. A system for improving latency during active state power management, wherein the system comprises:

an interface having a power management feature, wherein the power management feature comprises a low power PCI-E state and a full power PCI-E state; and

a controller for instructing the interface to initiate a transition from the low power PCI-E state to the full power PCI-E state, wherein the controller anticipates a requirement for the full power PCI-E state.

16. The system in claim 15, wherein the controller is an Ethernet MAC.

17. The system in claim 15, wherein the controller is a WLAN controller.

18. The system in claim 15, wherein the controller determines that a packet has passed address filtering prior to initiating the transition from the low power PCI-E state to the full power PCI-E state.

19. The system in claim 18, wherein the controller generates a delay between the anticipation of the full power PCI-E state requirement and the initiation of the transition.

20. The system in claim 19, wherein the delay is based on time.

21. The system in claim 19, wherein the delay is based on an amount of data received.

22. The system in claim 21, wherein the delay is based on the amount of data received relative to the total amount of data in the packet.

23. The system in claim 15, wherein the controller is operable at one or more speeds.

24. The system in claim 23, wherein the time between anticipating the requirement and initiating the transition is determined according to the speed at which the controller is operating.

25. A system for reducing transitions during active state power management, wherein the system comprises:

an interface having a power management feature; and

a controller for resetting an inactivity timer when a DMA transaction is anticipated.