Circuit Providing Low-Noise Readout

• US 20090101798A1
• Filed: 05/23/2008
• Published: 04/23/2009
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: UTI Limited Partnership
• Original Assignee: UTI Limited Partnership
• Inventors: Jullien, Graham, Tam, Terence, Yadid-Pecht, Orly
• Granted Patent: US 9,609,243 B2
• Time in Patent Office: Days
• US Class Current: 250/208.100
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Systems, methods, and apparatuses that may be employed to reduce noise in an electronic circuit are described. Systems are provided that include a circuit, wherein the circuit is configured to provide an active reset technique and an active column sensor readout technique. Methods for reducing circuit noise are also provided. The methods include providing a circuit configured to perform an active reset technique and an active column sensor readout technique. The methods further provide that the active reset technique and the active column sensor readout technique are both performed by the circuit. An imaging apparatus is provided that includes an array of photo-sensitive pixels, wherein each of the pixels can include a circuit configured to provide an active reset technique and an active column sensor readout technique. The active reset technique and the active column sensor readout technique are executable on the circuit.

Claims

1. A system, comprising a circuit, wherein said circuit is configured to provide an active reset technique and an active column sensor readout technique.

2. The system of claim 1, wherein said active reset technique and said active column sensor readout technique are performed by said circuit autonomously during a reset phase or a sampling phase respectively.

3. The system of claim 1, wherein said active reset technique and said active column sensor readout technique share common circuitry.

4. The system of claim 3, wherein said shared common circuitry is configured as an amplifier.

5. The system of claim 4, wherein said amplifier is partitioned between pixel circuitry and column circuitry.

6. The system of claim 4, wherein said amplifier is configurable to provide necessary input terminal polarity to accomplish an active reset technique or an active column sensor readout technique.

7. The system of claim 3, wherein said amplifier is a folded cascode amplifier.

8. The system of claim 6, wherein an operational configuration of said amplifier is controlled by a control signal.

9. The system of claim 6, wherein said amplifier performs said active reset technique or said active column sensor readout technique based on an input control signal.

10. The system of claim 4, wherein said amplifier is configured in a unity gain mode of operation during said active column sensor technique and configured as a high gain amplifier during said active reset technique.

11. The system of claim 1 wherein said active reset technique is preceded by hard reset.

12. The system of claim 1 wherein said system is an imaging system.

13. The system of claim 12, wherein said imaging system is a complementary metal oxide semiconductor, active pixel sensor imaging system.

14. The system of claim 13, wherein pixels contained in said active pixel sensor imaging system are read using a rolling shutter readout technique.

15. A method for reducing circuit noise, comprising:

providing a circuit configured to perform an active reset technique and an active column sensor readout technique;

wherein said active reset technique and said active column sensor readout technique are both performed by said circuit.

16. The method of claim 15, wherein said circuit is configured as an amplifier.

17. The method of claim 16, wherein said active reset technique is used to decrease ambiguity in reset voltage, and said active column sensor readout technique is used to decrease pixel level gain fixed pattern noise.

18. The method of claim 16, wherein said active reset technique is used to decrease reset noise, and said active column sensor readout technique is used to decrease pixel level gain fixed pattern noise.

19. The method of claim 17, wherein said active reset technique is used during a reset phase, and said active column sensor readout technique is used during a sampling phase.

20. The method of claim 16, wherein an input terminal polarity to said amplifier determines whether said amplifier performs said active reset technique or said active column sensor technique.

21. The method of claim 17, wherein said amplifier is configured in a unity gain mode of operation during said active column sensor readout technique and configured as a high gain amplifier during said active reset technique.

22. The method of claim 16, wherein said amplifier is a folded cascode amplifier.

23. The method of claim 21, wherein said high gain amplifier increases an effective capacitance for suppression of thermal reset noise.

24. The method of claim 16, wherein a feedback reset loop is disabled during said active column sensor readout technique, thereby reverting to a lower effective capacitance dominated by a photodiode capacitance, permitting a high charge-to-voltage gain/sensitivity for readout.

25. An imaging apparatus comprising an array of photo-sensitive pixels, wherein each of said pixels comprises a circuit configured to provide an active reset technique and an active column sensor readout technique, wherein said active reset technique and said active column sensor readout technique are executable on said circuit.

26. An imaging apparatus comprising:

(a) an array of imaging pixels, said imaging pixels being arranged in rows and columns, wherein each imaging pixel comprises a light-sensitive photodiode, a reset transistor, a switch in a feedback path, at least one transistor of a differential pair of transistors belonging to a partitioned amplifier having a plurality of transistors, and a row select transistor; and

(b) peripheral circuitry comprising transistors of said partitioned amplifier, and multiplexers;

wherein said partitioned amplifier is configurable as means for implementing an active reset technique in one phase of imaging, and configurable as a means for implementing an active column sensor readout technique in another phase of imaging.

27. The apparatus of claim 26 wherein said partitioned amplifier comprises a single-stage, differential-input, single-output, amplifier with an active current mirror.

28. The apparatus of claim 26 wherein said peripheral circuitry services imaging pixels within a column, and wherein at least one transistor of said differential pair of transistors belonging to said partitioned amplifier and said row select transistor of a plurality of imaging pixels are connected in parallel to a remainder of common, partitioned amplifier circuitry at said periphery.

29. The apparatus of claim 26 wherein said partitioned amplifier comprises a first branch and a second branch, wherein said first branch serves as an amplifier output during a reset phase, and said second branch serves as an amplifier output during a readout phase.

30. The apparatus of claim 26 wherein said switch comprises a pass transistor or a transmission gate.

31. The apparatus of claim 30 wherein said row select transistor and said switch of an imaging pixel are activated by a same row select control signal.

32. The apparatus of claim 30 wherein said row select control signal determines which row of imaging pixels within said array are connected to said peripheral circuitry.

33. The apparatus of claim 26 wherein a multiplexer establishes said feedback path for active reset, connecting a corresponding amplifier output to a gate of said reset transistor via said switch in said feedback path.

34. The apparatus of claim 26 wherein a multiplexer establishes a unity gain feedback loop for active column sensor readout, connecting said corresponding amplifier output to a negative input terminal of said partitioned amplifier.

35. The apparatus of claim 26 wherein a multiplexer controls an input terminal polarity of said partitioned amplifier by specifying an orientation of an active current mirror.

36. The apparatus of claim 33, 34, or 35 wherein said multiplexer comprises pass transistors or transmission gates.

37. The apparatus of claim 26 wherein a polarity of an input terminal of said partitioned amplifier coupled to a node of said photodiode is toggled by connecting a common gate node of an active current mirror contained in peripheral circuitry to either corresponding branch nodes of said amplifier, thereby defining an input current branch and an output current branch of said active current mirror.

38. The apparatus of claim 37 wherein said corresponding branch node of the output current branch of said active current mirror is said amplifier output.