NOVEL METHOD FOR FOUR DIRECTION LOW CAPACITANCE ESD PROTECTION

• US 20090101937A1
• Filed: 12/23/2008
• Published: 04/23/2009
• Est. Priority Date: 07/29/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Jian-Hsing, Chen, Shui-Hunyi
• Granted Patent: US 7,910,999 B2
• Time in Patent Office: Days
• US Class Current: 257/137
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Claims

1. A low capacitance device structure with associated parasitic bipolar transistors on a substrate for the purpose of providing four-way electrostatic voltage discharge protection to the active semiconductor devices connected to the I/O logic circuit line and including ESD protection of the power bus system comprising:

a first doped region with contact area of opposite dopent than said substrate;

isolation elements within said substrate;

a first FET gate element upon said substrate surface

a second doped region within said first doped region of opposite dopent than said first doped region;

a plurality of third, fourth and fifth doped regions within said substrate of similar dopent to said substrate;

a plurality of sixth and seventh doped regions within said substrate of similar dopent to said substrate;

an electrical connection system for said plurality of doped region and said FET gate;

a surface passivation layer for said ESD protection device.

2. The structure according to claim 1 wherein said substrate consists of silicon semiconductor material doped with an acceptor element such as boron to a concentration between 1E15 and 1E16 a/cm³.

3. The structure according to claim 1 wherein said first doped region is doped with a donor element such as phosphorous to form an N-well with a dopent concentration of between 1E16 and 1E18 a/cm³.

4. The structure according to claim 1 wherein said isolation elements consist of shallow trench isolation structure or thick field oxide structures.

5. The structure according to claim 1 wherein said gate element is comprised of an oxide insulator and a conductor element such as doped polysilicon.

6. The structure according to claim 1 wherein said second doped region is doped with an acceptor element such as boron to a density between 1E19 and 1E21 a/cm³ and forms the P+ anode terminal of an SCR device.

7. The structure according to claim 1 wherein said plurality of said third, fourth and fifth doped regions are doped with a donor dopent such as As to a density of between 1E20 and 1E21 a/cm³ to form N+ regions.

8. The structure according to claim 1 wherein said third doped regions form a N+ guard ring around said SCR device and said fourth doped region forms said SCR cathode and said fifth doped regions form the source and drain regions adjacent to said FET gate element to form a NFET device.

9. The structure according to claim 1 wherein said sixth and seventh doped regions are doped with an acceptor element such as boron to form P+ regions.

10. The structure according to claim 1 wherein said sixth doped region forms a first P+ guard ring interposed between said SCR device and said N+ guard ring, and said seventh doped region forms a second P+ guard ring around said NFET.

11. The structure according to claim 1 wherein said electrical connection system for said plurality of doped regions and said gate element consists of aluminum metallurgy or aluminum doped with 1% silicon metallurgy.

12. The structure according to claim 1 wherein said first and second P+ guard rings and said SCR cathode and said NFET drain and gate elements are connected by said conductor system to a second voltage source, typically ground.

13. The structure according to claim 1 wherein said SCR anode region and said N-Well contact region are connected by said conductor system to said I/O logic circuit line.

14. The structure according to claim 1 wherein said N+ guard ring and said NFEY source region are connected by said conductor system to a first voltage source, Vcc.

15. The structure according to claim 1 wherein said surface passivation layer is comprised of borosilicate glass or boron phosphosilicate glass.