PACKAGED SEMICONDUCTOR ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS

• US 20090102002A1
• Filed: 01/04/2008
• Published: 04/23/2009
• Est. Priority Date: 10/23/2007
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Jiang, Tongbi, Chia, Yong Poo
• Application Number:
  US11/969,613
• Publication Number:
  US 20090102002A1
• Time in Patent Office: Days
• US Class Current: 257/433
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Semiconductor packages, packaged semiconductor devices, methods of manufacturing semiconductor packages, methods of packaging semiconductor devices, and associated systems are disclosed. A semiconductor package in accordance with a particular embodiment includes a die having a first side carrying a first bond site electrically connected to a sensor and/or a transmitter configured to receive and/or transmit radiation signals. The semiconductor package also includes encapsulant material at least partially encapsulating a portion of the die. The semiconductor package includes a conductive path from the first bond site to a second bond site, positioned on a back surface of the encapsulant, which can include through-encapsulant interconnects. A cover can be positioned adjacent to the die and be generally transparent to a target wavelength.

Claims

1. A semiconductor system, comprising:

a semiconductor package that includes;

a die with a first side, a second side facing opposite from the first side, a first bond site toward the first side, and a sensor/transmitter coupled to the first bond site and positioned to receive/transmit a target radiation wavelength along a radiation path;

a cover generally transparent to the target wavelength and positioned transverse to the radiation path;

an encapsulant at least partially encapsulating the die, the encapsulant having a front surface generally flush with the first side and a back surface facing opposite from the front surface;

a second bond site positioned toward the back surface;

a via extending through the encapsulant; and

a conductive path coupled between first and second bond sites and including a conductive material disposed in the via.

2. The system of claim 1 wherein the back surface is offset from the second side of the die.

3. The system of claim 1 wherein the back surface is generally flush with the second side of the die.

4. The system of claim 1 wherein the conductive path includes a conductive redistribution layer electrically coupling the first bond site to the conductive material disposed in the via.

5. The system of claim 1 wherein the conductive path includes a conductive redistribution layer electrically coupling the second bond site to the conductive material disposed in the via.

6. The system of claim 5 wherein the encapsulant is the only dielectric material between the die and the conductive redistribution layer.

7. The system of claim 1 wherein the second bond site is located laterally outside a width of the die.

8. The system of claim 1 wherein the encapsulant is the only dielectric material between the die and the conductive material in the via.

9. The system of claim 1 wherein the package further includes—

a plurality of dies spaced apart from one another by gaps, the individual dies having a first bond site electrically coupled to a sensor/transmitter;

encapsulant in the gaps and at least partially encapsulating the dies to form a molded encapsulant volume; and

a plurality of vias extending through the molded encapsulant volume in the gaps, and wherein the conductive material is in the vias.

10. The system of claim 9, further comprising a conductive redistribution structure electrically coupling the individual first bond sites and the conductive material disposed in the individual vias.

11. The system of claim 9 wherein the individual vias include an encapsulant void having side walls, and wherein at least a portion of the side walls include a conductive coating electrically coupled to the individual first bond sites.

12. The system of claim 9 wherein the cover is sized to overlay at least the molded encapsulant volume.

13. A system of claim 1, further including a memory and a processor, and wherein the semiconductor package is operatively coupled to at least one of the memory and the processor.

14. A semiconductor system, comprising:

a semiconductor package that includes;

a die having a first side, a second side facing opposite from the first side, die walls extending between the first side and second side, and a first bond site at the first side, and wherein the die includes at least one of a sensor positioned to receive radiation along a radiation path at a target wavelength, and a transmitter configured to transmit radiation along the radiation path at the target wavelength;

a molded support structure formed of encapsulant in direct contact with the die, the molded support structure having a front surface generally flush with the first side, a back surface opposite the front surface, and a plurality of exterior side walls extending between the front surface and the back surface;

a conductive material applied to at least a portion of the molded support structure at the front surface, the back surface, and exterior side walls to form a conductive path from the first bond site to a second bond site at least proximate to the back surface; and

a cover at least generally transparent to the target wavelength and positioned transverse to the radiation path.

15. The system of claim 14 wherein a thickness of the die is less than a thickness of the molded support structure.

16. The system of claim 14 wherein a thickness of the die is generally the same as a thickness of the molded support structure, and wherein the second bond site is positioned at one of the back surface and the second side.

17. The system of claim 14 wherein the encapsulant is the only dielectric material between the conductive material at the exterior side walls and the die.

18. The system of claim 14 wherein a portion of the molded support structure is between the die and the conductive path along the die walls, and wherein the package includes no passivation layer adjacent to the encapsulant at the exterior side walls.

19. The system of claim 14 wherein a portion of the molded support structure is between the die and the conductive path along the die walls and the second side, and wherein the package includes no passivation layer adjacent to the encapsulant at the exterior side walls and the back surface.

20. The system of claim 14 wherein the second bond site is at the back surface located inwardly from the conductive material at the exterior side walls and laterally outside a width of the die.

21. The system of claim 14, further including a memory and a processor, and wherein the semiconductor package is operatively coupled to at least one of the memory and the processor.

22. A method for packaging a semiconductor die, comprising:

encapsulating a portion of the semiconductor die with encapsulant material to form an encapsulant body, the encapsulant body having a front surface, a back surface opposite the front surface, and an exposed outer edge between the front surface and the back surface, wherein the semiconductor die includes a sensor/transmitter configured to receive/transmit radiation at a target wavelength along a radiation path, the sensor/transmitter electrically coupled to a first bond site at an active side of the die;

positioning a cover transverse to the radiation path, wherein the cover is generally transparent to the target wavelength;

removing a portion of the encapsulant body between the back surface and the front surface to form a via through the encapsulant material; and

forming a conductive path from the first bond site at the active side to the back surface of the encapsulant body, the conductive path including conductive material disposed in the via.

23. The method of claim 22, further comprising:

supporting the active side of the semiconductor die on a carrier substrate before encapsulating a portion of the semiconductor die; and

after encapsulating a portion of the semiconductor die, removing the carrier substrate to expose the active side of the semiconductor die.

24. The method of claim 22 wherein forming the conductive path includes electrically connecting the first bond site to a second bond site, the second bond site positioned laterally outside a width of the semiconductor die for electrically coupling external elements.

25. The method of claim 22 wherein forming a conductive path includes coupling a conductive redistribution layer between the first bond site and the conductive material disposed in the via.

26. The method of claim 22 wherein:

encapsulating a portion of the semiconductor die includes applying the encapsulant material directly to the die without an intermediate dielectric material; and

forming a conductive path includes applying conductive material directly to the encapsulant body without intermediate dielectric material.

27. The method of claim 26 wherein:

encapsulating the portion of the semiconductor die includes molding the encapsulant material around a plurality of dies separated from each other by gaps;

removing a portion of the encapsulant body includes forming at least one via in individual gaps; and

the method further comprises cutting through the vias to separate neighboring packaged semiconductor dies from each other and exposing the conductive layer on at least a portion of the exposed outer edge of the encapsulant body.

28. The method of claim 22 wherein encapsulating the portion of the semiconductor die includes forming the encapsulant body around a plurality of dies separated from each other by gaps, the gaps filled with encapsulant material, and wherein the method further comprises:

forming a first conductive redistribution layer at the front surface electrically coupled to individual die first bond sites;

removing a portion of the encapsulant material in the gaps to form a plurality of vias through the encapsulant body;

filling individual vias with conductive material to form through-encapsulant interconnects terminating at the first conductive redistribution layer;

forming a second conductive redistribution layer at the back surface to electrically couple the through-encapsulant interconnects to a second bond site, the second bond site positioned to be electrically connected to external elements; and

cutting through at least the encapsulant material in the gaps to singulate a packaged semiconductor device.

29. The method of claim 22, further comprising testing the semiconductor die before encapsulating the semiconductor die, and wherein encapsulating the semiconductor die includes encapsulating only a known good die.

30. A method of manufacturing packaged semiconductor assemblies, comprising:

attaching a plurality of singulated dies to a temporary carrier, the dies being spaced apart from one another by gaps, wherein individual dies have an active side attached to the temporary carrier and a second side facing opposite the active side, and wherein the dies include a sensor/transmitter positioned along a radiation path;

placing an encapsulant material in the gaps and at least partially around the second side to form a molded volume, the molded volume having a front surface and a back surface;

positioning a cover transverse to the radiation path, the cover being generally transparent to a target wavelength receivable/transmittable by the sensor/transmitter; and

forming a plurality of conductive paths through the encapsulant material in the gaps between the front surface and the back surface.

31. The method of claim 30 wherein the conductive paths include a conductive interconnect through the molded volume between the front surface and the back surface, and wherein the individual dies have a first bond site at the active side, the first bond site being electrically coupled to the sensor/transmitter, and the method further includes electrically coupling the first bond site to the conductive interconnect to form the conductive path from the active side to the back surface.

32. The method of claim 31, further comprising positioning a second bond site at the back surface, the second bond site electrically coupled to the conductive interconnect.

33. The method of claim 30 wherein forming a plurality of conductive paths includes removing encapsulant material from at least a portion of the molded volume in the gaps to form encapsulant voids, and filling the encapsulant voids with conductive material.

34. The method of claim 30, further comprising cutting at least the encapsulant material in the gaps to singulate the packaged semiconductor assemblies.

35. The method of claim 30, further comprising removing encapsulant material from the back surface to thin the molded volume.

36. The method of claim 30 wherein forming a plurality of conductive paths includes—

removing encapsulant material from at least a portion of the molded volume in the gaps to form encapsulant voids having side walls;

disposing a conductive layer on at least a portion of the side walls; and

cutting along dicing streets and through the encapsulant voids to separate individual encapsulated dies.

37. The method of claim 30 wherein forming a plurality of conductive paths includes—

cutting through the encapsulant material in the gaps to separate individual encapsulated dies, the encapsulated dies having exposed edges between the front surface and the back surface; and

disposing a conductive layer on at least the exposed edges.