Lateral Power Diode with Self-Biasing Electrode

• US 20090102007A1
• Filed: 12/24/2008
• Published: 04/23/2009
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Christopher Boguslaw Kocon
• Inventors: Kocon, Christopher Boguslaw
• Granted Patent: US 8,125,029 B2
• Time in Patent Office: Days
• US Class Current: 257/471
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor diode includes a drift region of a first conductivity type and an anode region of a second conductivity type in the drift region such that the anode region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type extends in the drift region, and is laterally spaced from the anode region such that upon biasing the semiconductor power diode in a conducting state, a current flows laterally between the anode region and the first highly doped silicon region through the drift region. A plurality of trenches extends into the drift region perpendicular to the current flow. Each trench includes a dielectric layer lining at least a portion of the trench sidewalls and also includes at least one conductive.

Claims

1. A semiconductor diode comprising:

a drift region of a first conductivity type;

an anode region of a second conductivity type in the drift region, the anode region and the drift region forming a pn junction therebetween;

a first highly doped silicon region of the first conductivity type in the drift region, the first highly doped silicon region being laterally spaced from the anode region such that upon biasing the semiconductor power diode in a conducting state, a current flows laterally between the anode region and the first highly doped silicon region through the drift region; and

a plurality of trenches extending into the drift region perpendicular to the current flow, each trench having a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

2. The semiconductor diode of claim 1 wherein each conductive electrode electrically contacts the drift region along upper sidewalls of each trench.

3. The semiconductor diode of claim 2 wherein the drift region extends over a second silicon region of the first conductivity type, the second silicon region having a higher doping concentration than the drift region.

4. The semiconductor diode of claim 1 wherein each conductive electrode electrically contacts the drift region along a bottom of each trench.

5. The semiconductor diode of claim 1 wherein the drift region extends over a second silicon region, the second silicon region having a lower doping concentration than a doping concentration of the drift region, wherein the plurality of trenches extend through the drift region and terminate within the second silicon region, the conductive electrode in each trench electrically contacting the second silicon region along a bottom of each trench.

6. The semiconductor diode of claim 5 wherein the second silicon region extends over a dielectric layer.

7. The semiconductor diode of claim 1 wherein the drift region extends over a dielectric layer.

8. The semiconductor diode of claim 1 wherein each conductive electrode is of a second conductivity type.

9. The semiconductor diode of claim 1 wherein the plurality of electrodes is located between the anode region and the first highly doped silicon region in a staggered configuration.

10. The semiconductor diode of claim 1 further comprising a highly conductive plug extending into the first highly doped silicon region.

11. The semiconductor diode of claim 10 wherein the highly conductive plug and the plurality of trenches extend to substantially the same depth.

12. A schottky diode comprising:

a drift region of a first conductivity type;

a lightly doped silicon region of the first conductivity type in the drift region;

a conductor layer over and in contact with the lightly doped silicon region, the conductor layer forming a schottky contact with the lightly doped silicon region;

a highly doped silicon region of the first conductivity type in the drift region, the highly doped silicon region being laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region; and

a plurality of trenches extending into the drift region perpendicular to the current flow, each trench having a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

13. The schottky diode of claim 12 wherein each conductive electrode electrically contacts the drift region along upper sidewalls of each trench.

14. The schottky diode of claim 13 wherein the drift region extends over a silicon region of the first conductivity type, the silicon region having a higher doping concentration than the drift region.

15. The schottky diode of claim 12 wherein each conductive electrode electrically contacts the drift region along a bottom of each trench.

16. The schottky diode of claim 12 wherein the drift region extends over a silicon region, the silicon region having a lower doping concentration than a doping concentration of the drift region, wherein the plurality of trenches extend through the drift region and terminate within the silicon region, the conductive electrode in each trench electrically contacting the silicon region along a bottom of each trench.

17. The schottky diode of claim 16 wherein the silicon region extends over a dielectric layer.

18. The schottky diode of claim 12 wherein the drift region extends over a dielectric layer.

19. The schottky diode of claim 12 wherein each conductive electrode is of a second conductivity type.

20. The schottky diode of claim 12 wherein the plurality of electrodes are located between the lightly doped silicon region and the highly doped silicon region in a staggered configuration.

21. The schottky diode of claim 12 further comprising a highly conductive plug extending into the highly doped silicon region.

22. The schottky diode of claim 21 wherein the highly conductive plug and the plurality of trenches extend to substantially the same depth.

23. A method of forming a semiconductor diode comprising:

forming an anode region in a drift region of a first conductivity type, the anode region being of a second conductivity type, the anode region and the drift region forming a pn junction therebetween;

forming a first highly doped silicon region of the first conductivity type in the drift region, the first highly doped silicon region being laterally spaced from the anode region such that upon biasing the semiconductor power diode in a conducting state, a current flows laterally between the anode region and the first highly doped silicon region through the drift region;

forming a plurality of trenches extending into the drift region perpendicular to the current flow;

forming a dielectric layer lining at least a portion of each trench sidewalls; and

forming at least one conductive electrode in each trench.

24. The method of claim 23 wherein the dielectric layer is formed such that each conductive electrode electrically contacts the drift region along upper sidewalls of each trench.

25. The method of claim 24 further comprising forming an epitaxial layer over a substrate of the first conductivity type, the epitaxial layer forming the drift region, and the substrate having a higher doping concentration than the drift region.

26. The method of claim 23 wherein the dielectric layer is formed such that each conductive electrode electrically contacts the drift region along a bottom of each trench.

27. The method of claim 23 wherein the step of forming at least one conductive electrode comprises forming a polysilicon layer filling the plurality of trenches, the polysilicon layer being in-situ doped to have a second conductivity type.

28. A method of forming a schottky diode, comprising:

a lightly doped silicon region of a first conductivity type in a drift region of the first conductivity type;

forming a conductor layer over and in contact with the lightly doped silicon region, the conductor layer forming a schottky contact with the lightly doped silicon region;

forming a highly doped silicon region of the first conductivity type in the drift region, the highly doped silicon region being laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region;

forming a plurality of trenches extending into the drift region perpendicular to the current flow;

forming a dielectric layer lining at least a portion of each trench sidewalls; and

forming at least one conductive electrode in each trench.

29. The method of claim 28 wherein the dielectric layer is formed such that each conductive electrode electrically contacts the drift region along upper sidewalls of each trench.

30. The method of claim 29 further comprising forming an epitaxial layer over a substrate of the first conductivity type, the epitaxial layer forming the drift region, and the substrate having a higher doping concentration than the drift region.

31. The method of claim 28 wherein the dielectric layer is formed such that each conductive electrode electrically contacts the drift region along a bottom of each trench.

32. The method of claim 28 wherein the step of forming at least one conductive electrode comprises forming a polysilicon layer filling the plurality of trenches, the polysilicon layer being in-situ doped to have a second conductivity type.