Through-Silicon Vias and Methods for Forming the Same

• US 20090102021A1
• Filed: 10/17/2007
• Published: 04/23/2009
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kai-Ming, Kuo, Chen-Cheng, Chen, Chen-Shien, Chen, Chih-Hua, Hsu, Kuo-Ching Steven
• Granted Patent: US 8,476,769 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.

Claims

1. An integrated circuit structure comprising:

a substrate;

a through-silicon via (TSV) extending into the substrate;

a TSV pad spaced apart from the TSV; and

a metal line over, and electrically connecting, the TSV and the TSV pad.

2. The integrated circuit structure of claim 1 further comprising an insulating layer separating the TSV from the substrate.

3. The integrated circuit structure of claim 2, wherein the TSV comprises a diffusion barrier layer adjoining the insulating layer.

4. The integrated circuit structure of claim 1 further comprising dielectric layers between the substrate and the metal line, wherein the TSV penetrates through the dielectric layers.

5. The integrated circuit structure of claim 1, wherein the TSV pad comprises a different material from the metal line.

6. The integrated circuit structure of claim 1, wherein the TSV is horizontally on only one side of the TSV pad.

7. The integrated circuit structure of claim 1 further comprising:

a bond pad; and

a solder mask covering the TSV pad and the metal line, wherein the bond pad is exposed through the solder mask.

8. The integrated circuit structure of claim 1 further comprising a conductive layer on a back surface of the substrate and electrically connected to the TSV.

9. The integrated circuit structure of claim 1, wherein the metal line and an inner portion of the TSV comprises a same material and form a continuous region.

10. An integrated circuit structure comprising:

a semiconductor substrate;

a plurality of dielectric layers over the semiconductor substrate;

a through-silicon via (TSV) penetrating the plurality of dielectric layers and the semiconductor substrate, wherein the TSV extends to a back surface of the semiconductor substrate;

a TSV pad directly over the plurality of dielectric layers, wherein the TSV pad is horizontally on only one side of the TSV pad; and

a metal line overlying and electrically connecting the TSV pad and the TSV.

11. The integrated circuit structure of claim 10, wherein the metal line comprises a same material as an inner portion of the TSV.

12. The integrated circuit structure of claim 10 further comprising an insulating layer separating the TSV and the metal line from the semiconductor substrate and the plurality of dielectric layers, wherein the TSV is electrically connected to the metal line through an opening in the insulating layer.

13. The integrated circuit structure of claim 12, wherein the TSV comprises a diffusion barrier layer adjoining the insulating layer.

14. The integrated circuit structure of claim 10 further comprising a solder mask overlying the metal line.

15. The integrated circuit structure of claim 10 further comprising a bond pad in a same dielectric layer as the TSV pad, wherein the solder mask comprises an opening exposing the bond pad.

16. The integrated circuit structure of claim 10 further comprising a conductive layer on a back surface of the semiconductor substrate, wherein the TSV is electrically connected to the conductive layer.

17. A method of forming an integrated circuit structure, the method comprising:

providing a wafer comprising;

a semiconductor substrate; and

a through-silicon via (TSV) pad over the semiconductor substrate;

forming a TSV opening extending from a top surface of the wafer into the semiconductor substrate, wherein the TSV opening is spaced apart from the TSV pad;

forming a TSV in the TSV opening; and

forming a metal line electrically connecting the TSV and the TSV pad.

18. The method of claim 17, wherein the step of forming the TSV in the TSV opening comprises:

blanket forming a mask covering the wafer;

patterning the mask to expose the TSV opening, the TSV pad, and a region therebetween;

selectively filling a conductive material into the TSV opening to form the TSV, until a portion of the conductive material higher than a top surface of the TSV electrically connects the TSV pad and the TSV; and

removing the mask.

19. The method of claim 18 further comprising, before the step of selectively filling the conductive material, blanket forming an insulating material, and patterning the insulating material to expose the TSV pad.

20. The method of claim 17 further comprising forming a solder mask covering the metal line.

21. The method of claim 20, wherein the wafer further comprises a bond pad in a same dielectric layer as the TSV pad, and wherein the method further comprises patterning the solder mask to expose the bond pad.

22. The method of claim 17 further comprising grinding a back surface of the wafer to expose the TSV through the back surface of the wafer.

23. The method of claim 22 further comprising, after the step of grinding, forming a conductive layer on the back surface of the wafer, wherein the conductive layer is electrically connected to the TSV.

24. A method of forming an integrated circuit structure, the method comprising:

providing a wafer comprising;

a semiconductor substrate; and

a through-silicon via (TSV) pad over the semiconductor substrate;

blanket forming a diffusion barrier layer over the wafer, wherein the diffusion barrier layer extends into a TSV opening;

blanket forming a copper seed layer on the diffusion barrier layer;

forming and patterning a mask layer, wherein the TSV pad, the TSV opening, and a region therebetween are exposed through the mask layer;

selectively forming a copper layer on the copper seed layer, wherein the copper layer fills the TSV opening to form a TSV, and wherein the copper layer extends over the TSV pad;

removing the mask layer to expose portions of the copper seed layer and the diffusion barrier layer underlying the mask layer;

etching the exposed portions of the copper seed layer; and

etching the exposed portions of the barrier layer.

25. The method of claim 24 further comprising:

applying an ultra-violet glue on a top surface of the wafer;

mounting a glass wafer on the wafer using the ultra-violet glue; and

grinding a backside of the wafer to expose the TSV.

26. The method of claim 24, wherein the copper seed layer is formed using sputtering, and wherein the copper layer is formed using plating.

27. The method of claim 24 further comprising, before the step of forming the diffusion barrier layer, forming an insulating layer, and patterning the insulating layer to expose the TSV pad.