Semiconductor Device

• US 20090102029A1
• Filed: 10/17/2008
• Published: 04/23/2009
• Est. Priority Date: 10/19/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Tadaoka, Akihiko
• Granted Patent: US 8,030,766 B2
• Time in Patent Office: Days
• US Class Current: 257/673
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A semiconductor device that can cope with larger numbers of pins and finer pitches while suppressing lowering of the manufacturing yield and reliability includes: a semiconductor chip having a plurality of electrodes provided on an upper surface thereof; a plurality of lead terminals including inner lead portions disposed toward the semiconductor chip; a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and a sealing-resin layer for sealing at least the semiconductor chip, the inner lead portions and the wiring member. The electrodes of the semiconductor device and the inner lead portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a plurality of electrodes provided on a surface on one side thereof;

a plurality of lead terminals having one end portions thereof disposed toward the semiconductor chip;

a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and

a sealing-resin layer for sealing at least the semiconductor chip, the one end portions of the lead terminals and the wiring member, wherein

the electrodes of the semiconductor chip and the one end portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.

2. The semiconductor device of claim 1, wherein

a metal bump is formed on the electrodes of the semiconductor chip and on the one end portions of the lead terminals.

3. The semiconductor device of claim 2, wherein

the metal bump is a stud bump.

4. The semiconductor device of claim 1, wherein

the sheet-form wiring member includes a sheet-form polyimide member.

5. The semiconductor device of claim 2, wherein

the sheet-form wiring member includes a sheet-form polyimide member.

6. The semiconductor device of claim 1, wherein

upper surfaces of the one end portions of the lead terminals and the surface on the one side of the semiconductor chip are at substantially a same height in a thickness direction of the semiconductor chip.

7. The semiconductor device of claim 2, wherein

upper surfaces of the one end portions of the lead terminals and the surface on the one side of the semiconductor chip are at substantially a same height in a thickness direction of the semiconductor chip.

8. The semiconductor device of claim 1, wherein

the semiconductor chip is sealed in the sealing-resin layer so as to form a QFP type package.