ON-CHIP TEMPERATURE GRADIENT MINIMIZATION USING CARBON NANOTUBE COOLING STRUCTURES WITH VARIABLE COOLING CAPACITY

• US 20090102046A1
• Filed: 10/18/2007
• Published: 04/23/2009
• Est. Priority Date: 10/18/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Grill, Alfred, Georgiou, Christos John, Rogowitz, Bernice E., Dimitrakopoulos, Christos Dimitrios
• Granted Patent: US 8,063,483 B2
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the hot spot area and at least one bundle of additional nanotubes for cooling the intermediate temperature area, and having heat conductivity lower than the bundle of first nanotubes. The heat conductivity of both sets of the nanotubes is sufficient to decrease any temperature gradient between the defined hot spot area, the defined intermediate temperature area, and at least one lower temperature area on the die. The walls of the first nanotubes and the additional nanotubes are surrounded by a heat conducting matrix material operatively associated with the lower temperature area.

Claims

1. A semiconductive device comprising a die wherein the die comprises:

(a) at least one defined hot-spot area lying in a plane on the die;

(b) at least one defined minimum temperature area comprising an area lying in a plane on the die and at a temperature lower than the temperature of the hot-spot area, wherein the minimum temperature area comprises the minimum temperature of the die;

(c) at least one defined intermediate temperature area comprising an area lying in a plane on the die at a temperature lower than the temperature of the hot-spot area;

(d) cooling means comprising at least one bundle of first nanotube means composed of a heat conducting material and extending in a direction outwardly from the plane of the hot-spot area, the first nanotube means being operatively associated with and in heat conducting relationship with the hot-spot area and having heat conductivity sufficient to decrease any temperature gradient between the hot-spot area and any other temperature areas on the die;

(e) cooling means comprising at least one bundle of additional nanotube means composed of a heat conducting material and extending in a direction outwardly from the plane of the intermediate temperature area, the additional nanotube means being operatively associated with and in heat conducting relationship with the intermediate temperature area and having heat conductivity sufficient to decrease any temperature gradient between the intermediate temperature area and any other temperature areas on the die;

(f) the heat conductivity of the bundle of first nanotube means being greater than the heat conductivity of the additional nanotube means;

(g) the bundle of first nanotube means and the bundle of additional nanotube means being substantially surrounded by a matrix material comprised of a heat conducting material operatively associated with and in heat conducting relation with the minimum temperature area;

(h) the heat conductivity of the bundle of first nanotube means and the bundle of additional nanotube means being greater than the heat conductivity of the matrix material;

(i) the distal ends of the bundle of first nanotube means and the bundle of additional nanotube means being positioned for direct contact with a medium comprising a heat exchange medium.

2. The device of claim 1 comprising the bundle of first nanotube means, the bundle of additional nanotube means and the matrix material wherein the bundle of first nanotube means are substantially parallel to one another;

and the bundle of additional nanotube means are substantially parallel to one another; and

the bundle of first nanotube means and the bundle of additional nanotube means substantially;

(a) are linear or helical;

(b) are perpendicular to the plane of the hot spot;

(c) comprise single wall or multi-wall nanotubes.

3. The device of claim 2 wherein the bundle of first nanotube means and the bundle of additional nanotube means have different arial densities on the device wherein the nanotube means having the higher arial density on the device cools the device at a rate higher than the nanotube means with the lower arial density on the device.

4. The device of claim 2 wherein the nanotubes in the bundle of first nanotube means and the nanotubes in the bundle of additional nanotube means have different diameters wherein the nanotube means having the smaller diameter nanotubes cools the device at a rate higher than the nanotube means with the larger diameter nanotubes.

5. The device of claim 2 wherein the matrix material comprises a metal material and the nanotube means comprises carbon.

6. The device of claim 2 comprising a VLSI device.

7. A processes for providing cooling means on the surface of a semiconducting device having a die comprising:

(a) defining by thermal analysis, at least one hot-spot area (a) lying in a plane on the die;

(b) defining by thermal analysis, at least one minimum temperature area (b) comprising a defined area lying in a plane on the die and at a temperature lower than the temperature of the defined hot-spot area, wherein the minimum temperature area comprises the minimum temperature of the die;

(c) defining by thermal analysis, at least one intermediate temperature area (c) comprising an area lying in a plane on the die at a temperature lower than the temperature of the defined hot-spot area.

(d) fabricating a mask (d) corresponding to the hot-spot area (a);

(e) selectively applying to the surface of the die by means of the mask (d), a catalyst to define a catalyst area (e) corresponding to the hot-spot area (a) and thereby produce a semiconductor device having a die with a selectively catalyzed surface (e) corresponding to hot-spot area (a);

the catalyst selected to promote the growth of a bundle of heat conducting first nanotube means;

(f) fabricating a mask (f) corresponding to the intermediate temperature area (c);

(g) selectively applying to the surface of the die by means of the mask (f) a second catalyst to define a catalyst area (g) corresponding to the intermediate temperature area (c) and there produce a semiconductor device having a die with a selectively catalyzed surface (g) corresponding to intermediate temperature area (c);

the second catalyst selected to promote growth of a bundle of heat conducting additional nanotube means;

(h) growing first nanotube means (h) from a heat conducting material and on the selectively catalyzed surface (e) corresponding to the hot-spot area (a) and to extend in a direction outwardly form the plane of the hot-spot area (a), the first nanotube means (h) being operatively associated with and in a heat conducting relationship with the hot-spot area (a) to decrease any temperature gradient between the hot-spot area (a) and other areas on the device;

(i) growing additional nanotube means (i) from a heat conducting material and on the selectively catalyzed surface area (g) corresponding to the intermediate temperature area (c) to extend outwardly from the plane of the intermediate temperature area (c), the additional nanotube means (i) being operatively associated with and in a heat conducting relationship with the intermediate temperature area (c) to decrease any temperature gradient between the intermediate temperature area (c) and other areas on the device;

(j) depositing a heat conducting matrix material (j) on the minimum temperature area (b), to form a matrix to surround the first nanotube means and the additional nanotube means, the heat conducting matrix material (j) extending to and operatively associated with the area (b) to conduct heat away from the area (b),

(k) the first nanotube means (h) and the additional nanotube means (i) made from heat conducting materials having a higher heat conductivity than the heat conducting matrix material, the heat conductivity of the first nanotube means (h) being greater than the heat conductivity of the additional nanotube means (i)

(i) providing for the distal ends of the first nanotube means and the additional nanotube means to be sufficiently exposed above the heat conducting matrix material (j) to make the distal ends available for direct contact with a medium comprising a heat exchange medium.

8. The process of claim 7 comprising the bundle of first nanotube means, the additional bundle of nanotube means and the matrix material wherein;

the bundle of first nanotube means comprise nanotubes substantially parallel to one another,

the bundle of additional nanotube means comprise nanotubes substantially parallel to one another; and

the first bundle of nanotube means and the bundle of additional nanotube means substantially;

(a) are linear or helical;

(b) are perpendicular to the plane of the hot spot;

(c) comprise single wall or multi-wall nanotubes.

9. The process of claim 7 comprising forming the bundle of first nanotube means and the bundle of additional nanotube means to have different surface densities on the device wherein the nanotube means having the higher arial density on the device cool the device at a rate higher than the nanotube means with the lower arial density on the device.

10. The process of claim 7 comprising forming the bundle of first nanotube means and the bundle of additional nanotube means to have different arial densities on the device by applying the catalyst as particles of catalyst on the die and controlling the spacing of the catalyst wherein the nanotube means having the higher surface density on the device cools the device at a-rate higher than the nanotube means with the lower surface density on the device.

11. The process of claim 10 wherein different sizes of catalyst particles are placed in different areas on the die for manufacturing said nanotubes.

12. The process of claim 10 comprising controlling the spacing of the catalyst by means of a SAM process.

13. The process of claim 7 comprising forming the matrix material from a metal material and the nanotube means from carbon.

14. The process of claim 7 wherein the device comprises a VLSI device.

15. The process of claim 7 wherein prior to selectively applying the catalyst layer to the surface of the die, the step of applying a metal adhesion layer to the surface of the die.

16. The process of claim 7 wherein the catalyst areas are patterned by nanostamping.

17. The process of claim 8 wherein the catalyst areas are patterned by nanostamping.

18. A product produced by the processes of claim 7.

19. A product produced by the processes of claim 16.

20. A product produced by the processes of claim 17.