SYSTEM AND METHOD TO MANUFACTURE AN IMPLANTABLE ELECTRODE

• US 20090102068A1
• Filed: 05/30/2008
• Published: 04/23/2009
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Neuronexus Technologies Incorporated (NEL Group, Inc.)
• Original Assignee: Neuronexus Technologies Incorporated (NEL Group, Inc.)
• Inventors: Gulari, Mayurachat, Hetke, Jamille Farraye, Kipke, Daryl R., Kong, K. C., Pellinen, David S., Vetter, Rio J.
• Granted Patent: US 8,241,950 B2
• Time in Patent Office: Days
• US Class Current: 257/787
• CPC Class Codes: A61N 1/05 for implantation or insertion into the body, e.g. heart electrode A61N1/06 takes precedence
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Claims

1. A method of building a series of encapsulated devices, the method comprising the steps of:

providing a base having a frame portion and a center portion;

building a preliminary structure coupled to the base;

removing a portion of the preliminary structure to define a series of devices and a plurality of bridges, wherein the series of devices are coupled to the center portion of the base, and wherein the plurality of bridges are coupled to the frame portion of the base and to the series of devices;

removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and

encapsulating the series of devices.

2. The method of claim 1 wherein the step of providing a base having a frame portion and a center portion includes the step of providing a silicon wafer.

3. The method of claim 1 wherein the step of providing a base having a frame portion and a center portion includes the step of removing a portion of the base such that the base defines a trench that separates the center portion of the base from the frame portion of the base.

4. The method of claim 3 wherein the step of removing a portion of the base such that the base defines a trench that separates the center portion of the base from the frame portion of the base is performed through a deep reactive ion etching (DRIE) process.

5. The method of claim 1 wherein the step of building a preliminary structure coupled to the base includes the step of building a plurality of layers coupled to the base.

6. The method of claim 5 wherein the step of building a plurality of layers coupled to the base includes the step of building a plurality of layers of material chosen from the group consisting of silicon, metal, polymer, and any combination thereof.

7. The method of claim 5 wherein the step of building a plurality of layers coupled to the base further includes the step of building an electrode site and a conductive lead.

8. The method of claim 7 further comprising the step of removing a portion of the encapsulation from the series of devices to expose the electrode site.

9. The method of claim 8 further comprising the step of electroplating the exposed electrode site.

10. The method of claim 1 wherein the step of removing a portion of the preliminary structure to define a series of devices and a plurality of bridges is performed through a reactive ion etching (RIE) process.

11. The method of claim 1 wherein the step of removing the center portion of the base such that the frame portion defines an open region includes the steps of creating a mask on the base and patterning the mask to expose the frame portion of the base.

12. The method of claim 11 wherein the step of removing the center portion of the base such that the frame portion defines an open region further includes the step of modifying the frame portion of the base such that it behaves as an etch stop.

13. The method of claim 12 wherein the step of modifying the frame portion of the base is performed through deep boron diffusion.

14. The method of claim 12 wherein the step of removing the center portion of the base such that the frame portion defines an open region is performed with a wet etchant that removes the unmodified portions of the base.

15. The method of claim 1 wherein the step of encapsulating the series of devices includes the step of encapsulating the series of devices, the plurality of bridges, and the frame portion of the base in a conformal coat of a coating.

16. The method of claim 1 further comprising the step of uncoupling the series of devices from the plurality of bridges and from the frame portion of the base.

17. A method of encapsulating a semiconductor device, the method comprising the steps of:

providing a wafer that defines an open region;

building a semiconductor device;

building a plurality of bridges coupled to the wafer and coupled to the semiconductor device such that the plurality of bridges suspend the semiconductor device in the open region defined by the wafer; and

encapsulating the semiconductor device.

18. The method of claim 17 wherein the step of providing a wafer that defines an open region includes the steps of:

providing a wafer having a frame portion and a center portion;

modifying the frame portion of the wafer such that it behaves as an etch stop; and

removing the center portion of the wafer such that the frame portion defines an open region.

19. The method of claim 17 wherein the steps of building a semiconductor device and building a plurality of bridges coupled to the wafer and coupled to the semiconductor device include the steps of:

building a preliminary structure coupled to the wafer; and

removing a portion of the preliminary structure to define a semiconductor device and a plurality of bridges.

20. The method of claim 19 wherein the step of building a preliminary structure coupled to the wafer includes the steps of:

building a plurality of layers coupled to the wafer; and

building an electrode site and a conductive lead.

21. The method of claim 17 wherein the step of encapsulating the semiconductor device includes the step of encapsulating the semiconductor device, the plurality of bridges, and the wafer in a conformal coat of a coating.

22. The method of claim 17 further comprising the step of uncoupling the semiconductor device from the plurality of bridges and from the wafer.

23. A semiconductor device encapsulation system, comprising:

a wafer that defines an open region;

a plurality of bridges coupled to the wafer that extend from the wafer into the open region; and

a semiconductor device coupled to the plurality of bridges such that the semiconductor device is suspended in the open region.

24. The semiconductor device encapsulation system of claim 23 further comprising a coating that encapsulates the semiconductor device.

25. The semiconductor device encapsulation system of claim 24 wherein the semiconductor device is removable from the plurality of bridges such that upon removal, the semiconductor device is encapsulated in a conformal coat of the coating.

26. The semiconductor device encapsulation system of claim 23 wherein the wafer is made of silicon.

27. The semiconductor device encapsulation system of claim 23 wherein the semiconductor device and the plurality of bridges include a same plurality of layers.

28. The semiconductor device encapsulation system of claim 27 wherein the material of each layer is chosen from the group consisting of silicon, metal, and polymer.

29. The semiconductor device encapsulation system of claim 27 wherein the semiconductor device further includes an electrode site and a conductive lead.