Comparator

• US 20090102516A1
• Filed: 09/19/2008
• Published: 04/23/2009
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Suzuki, Masaya, Kawai, Hirotaka, Tanaka, Yasuomi, Tsuji, Nobuaki
• Granted Patent: US 7,830,182 B2
• Time in Patent Office: Days
• US Class Current: 327/77
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence

Abstract

A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors.

Claims

1. A comparator comprising:

first and second field effect transistors which respectively include sources connected commonly with each other and gates to which first and second input voltages are supplied respectively;

a constant current source interposed between a common node connected between the sources of the first and second field effect transistors and a first power source;

third and fourth field effect transistors which respectively include sources connected to a second power source that differs in voltage from the first power source, gates connected to a drain of the first field effect transistor, and drains connected to respective drains of the first and second field effect transistors; and

a fifth field effect transistor which includes a source connected to a gate and a drain of the third-field effect transistor, a drain connected to a node connected between the respective drains of the second and fourth field effect transistors, and a gate connected to the node,

wherein a voltage of a node connected between the respective drains of the second and fourth field effect transistors is output as a signal showing a result of comparison between the first and second input voltages.

2. The comparator according to claim 1, wherein the voltage of the node connected between the respective drains of the second and fourth field effect transistors does not exceed a value obtained by the following expression:

V_3t+Δ

₃ov+V_5t+Δ

₅ov

where V_3t represents threshold values of the third field effect transistor, Δ

₃ov represents overdrive voltages of the third field effect transistor, V_5t represents threshold values of the fifth field effect transistor and Δ

₅ov represents overdrive voltages of the fifth field effect transistor.