Decentralised fault-tolerant clock pulse generation in vlsi chips
First Claim
1. A method for distributed, fault-tolerant clock pulse generation in hardware systems, particularly VLSI chips, systems-on-a-chip, IP cores, PCBs and PCB systems, characterized in thatthe system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs) without the use of external or internal clock oscillators, in whichi. an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults,ii. each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it,all local clock pulses are synchronized with respect to frequency in an assured manner, in the sense that any two local clock pulse signals differ from each other by a maximum of a specified, constant number of clock cycles within a given period of time, so that a global system clock pulse can be generated from any local clock pulse with the help of clock pulse conversion switching circuits, which global system clock pulse enables the global synchronous communication between any number of functional units on the chip,a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy,the system clock pulse automatically achieves the maximum possible frequency.
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Abstract
The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.
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Citations
8 Claims
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1. A method for distributed, fault-tolerant clock pulse generation in hardware systems, particularly VLSI chips, systems-on-a-chip, IP cores, PCBs and PCB systems, characterized in that
the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs) without the use of external or internal clock oscillators, in which i. an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, ii. each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, all local clock pulses are synchronized with respect to frequency in an assured manner, in the sense that any two local clock pulse signals differ from each other by a maximum of a specified, constant number of clock cycles within a given period of time, so that a global system clock pulse can be generated from any local clock pulse with the help of clock pulse conversion switching circuits, which global system clock pulse enables the global synchronous communication between any number of functional units on the chip, a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, the system clock pulse automatically achieves the maximum possible frequency.
Specification