Decentralised fault-tolerant clock pulse generation in vlsi chips

• US 20090102534A1
• Filed: 07/18/2005
• Published: 04/23/2009
• Est. Priority Date: 07/19/2004
• Status: Active Grant

• Current Assignee: Technische Universitã¤T Wien
• Original Assignee: Technische Universitã¤T Wien
• Inventors: Schmid, Ulrich, Steininger, Andreas
• Granted Patent: US 7,791,394 B2
• Time in Patent Office: Days
• US Class Current: 327/292
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware

Abstract

The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.

Claims

1. A method for distributed, fault-tolerant clock pulse generation in hardware systems, particularly VLSI chips, systems-on-a-chip, IP cores, PCBs and PCB systems, characterized in that

the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs) without the use of external or internal clock oscillators, in which

i. an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults,

ii. each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it,

all local clock pulses are synchronized with respect to frequency in an assured manner, in the sense that any two local clock pulse signals differ from each other by a maximum of a specified, constant number of clock cycles within a given period of time, so that a global system clock pulse can be generated from any local clock pulse with the help of clock pulse conversion switching circuits, which global system clock pulse enables the global synchronous communication between any number of functional units on the chip,

a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy,

the system clock pulse automatically achieves the maximum possible frequency.

2. A method as defined in claim 1, characterized in that the availability of the global system clock pulse depends only on the ratio of the maximum to minimum end-to-end signal delay of the signal path on the chip, but not, however, on its maximum.

3. A method as defined in claim 1 or claim 2, characterized in that the synchronization accuracy of the local clock pulses already active and thus of the global system clock pulse derived therefrom is also guaranteed during the power-up phase of the hardware.

4. A method as defined in any one of claims 1 to 2, characterized in that the implementation is effected with the aid of asynchronous logic.

5. A method as defined in any one of claims 1 to 2, characterized in that the stability of the global system clock pulse is enhanced by using variable delay elements or special clock pulse conversion circuits in the TS-Algs, wherein the current delay times or clock pulse correction values are obtained

statically at the time of manufacture and/or

configurably to the respective application of the chip at execution time, and/or

automatically on the basis of a one-time or continuous measurement of the operating parameters.

6. A method as defined in any one of claims 1 to 5, characterized in that pulse synchronization algorithms are used which guarantee pulse synchronization as early on as the reset of the functional units.

7. A method for global data transmission free from meta-stability problems between the various functional units of a hardware system, characterized in that frequency division of the clock pulse generated in distribution in accordance with the method defined in any one of claims 1 to 6 is carried out.

8. A hardware system for carrying out the method as defined in any one of claims 1 to 7, comprising two or more functional units (Fu1, Fu2, . . . ), wherein the system clock pulse is generated in distribution by a plurality of intercommunicating, fault-tolerant clock pulse synchronization algorithms (TS-Algs) without the use of external or internal clock oscillators, in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to permanent and transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it.