TIMING CONTROLLER, LIQUID CRYSTAL DISPLAY HAVING THE SAME, AND METHOD OF DRIVING LIQUID CRYSTAL DISPLAY

• US 20090102776A1
• Filed: 06/23/2008
• Published: 04/23/2009
• Est. Priority Date: 10/18/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Ko, Hyun-seok, Kim, Myeong-su
• Granted Patent: US 8,605,026 B2
• Time in Patent Office: Days
• US Class Current: 345/94
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2320/0646 Modulation of illumination source brightness and image signal correlated to each other
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2360/16 Calculation or use of calculated indices related to luminance levels in display data
• CPC Class Codes: G09G 3/3426 the different display panel areas being distributed in two dimensions, e.g. matrix
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A liquid crystal display includes a first timing controller for receiving image signals in synchronization with a first clock signal and outputting representative image signals in synchronization with a second clock signal, the frequency of the second clock signal being lower than the frequency of the first clock signal; and circuitry for controlling luminance of light-emitting blocks of the liquid crystal display in response to the representative image signals.

Claims

1. A liquid crystal display comprising:

a first timing controller for receiving image signals in synchronization with a first clock signal and outputting representative image signals in synchronization with a second clock signal, the frequency of the second clock signal being lower than the frequency of the first clock signal; and

circuitry for controlling luminance of light-emitting blocks of the liquid crystal display in response to the representative image signals.

2. The liquid crystal display of claim 1 wherein said circuit comprises:

a second timing controller for outputting backlight data signals corresponding to the representative image signals; and

a backlight driver for controlling luminance of light-emitting blocks in response to the backlight data signals.

3. The liquid crystal display of claim 2, wherein the first timing controller serially outputs the representative image signals to the second timing controller.

4. The liquid crystal display of claim 2, further comprising a display panel which is divided into a plurality of display blocks that correspond to the respective light-emitting blocks;

wherein the representative image signals are representative values of image signals received for the respective display blocks.

5. The liquid crystal display of claim 4, wherein the representative image signals are generated by the first timing controller which:

writes the representative image signals to a memory in synchronization with the first clock signal;

reads the representative image signals from the memory in synchronization with the second clock signal; and

serially outputs the representative image signals read out from the memory to the second timing controller.

6. The liquid crystal display of claim 4, wherein the first timing controller comprises:

a memory;

a representative-value generator for receiving the image signals, generating the representative image signals, and writing the representative image signals to the memory in synchronization with the first clock signal; and

a serializer for reading the representative image signals from the memory in synchronization with the second clock signal, and serially outputting the read representative image signals to the second timing controller.

7. The liquid crystal display of claim 6, wherein each representative image signal comprises a plurality of bits, and the serializer comprises:

a plurality of latch units for reading the representative image signals from the memory in synchronization with the second clock signal and storing the read representative image signals; and

a plurality of transfer units for performing bit-by-bit output of the representative image signals stored in the respective latch units.

8. The liquid crystal display of claim 7, wherein the serializer further comprises a multiplexer that serially transmits output bits of the transfer units.

9. The liquid crystal display of claim 4, wherein the first timing controller comprises:

a representative-value generator for receiving the image signals in synchronization with the first clock signal, and generating the representative image signals that correspond to the respective display blocks;

a plurality of latch units for storing the representative image signals; and

a transfer unit for performing bit-by-bit output of the representative image signals stored in the latch units, the bit-by-bit output being performed in synchronization with the second clock signal.

10. A timing controller comprising:

a representative-value generator for receiving a plurality of image signals in synchronization with a first clock signal and generating a plurality of representative image signals; and

a serializer for serially outputting the representative image signals in synchronization with a second clock signal, the frequency of the second clock signal being lower than the frequency of the first clock signal.

11. The timing controller of claim 10, further comprising a memory;

wherein the representative-value generator writes the representative image signals to the memory in synchronization with the first clock signal, and the serializer reads the representative image signals from the memory in synchronization with the second clock signal.

12. The timing controller of claim 11, wherein each representative image signal comprises a plurality of bits, and the serializer comprises:

a plurality of latch units for reading the respective representative image signals from the memory in synchronization with the second clock signal and storing the read representative image signals; and

a plurality of transfer units for performing bit-by-bit output of the representative image signals stored in the respective latch units.

13. The timing controller of claim 12, wherein the serializer further comprises a multiplexer for serially transmitting the output bits of the transfer units.

14. The timing controller of claim 10, wherein the serializer comprises:

a plurality of latch units for storing the respective representative image signals; and

a transfer unit for performing bit-by-bit output, in synchronization with the second clock signal, of the representative image signals stored in the respective latch units.

15. A method of driving a liquid crystal display including a liquid crystal display panel (LCD panel) and light-emitting blocks providing light to the LCD panel, the method comprising:

receiving image signals in synchronization with a first clock signal and outputting representative image signals in synchronization with a second clock signal, the frequency of the second clock signal being lower than the frequency of the first clock signal; and

controlling luminance of the light-emitting blocks in response to the representative image signals.

16. The method of claim 15 wherein controlling luminance of the light-emitting blocks in response to the representative image signals comprises:

providing backlight data signals corresponding to the representative image signals; and

controlling luminance of the light-emitting blocks in response to the backlight data signals.

17. The method of claim 16, wherein the outputting of the representative image signals in synchronization with the second clock signal comprises outputting the representative image signals in series.

18. The method of claim 16, wherein the LCD panel is subdivided into a plurality of display blocks which correspond to the respective light-emitting blocks, and the representative image signals are representative values of image signals provided to the respective display blocks.

19. The method of claim 18, wherein the outputting of the representative image signals in synchronization with the second clock signal comprises:

generating the representative image signals that correspond to the respective display blocks;

writing the representative image signals to a memory in synchronization with the first clock signal;

reading the representative image signals from the memory in synchronization with the second clock signal; and

serially outputting the read representative image signals.

20. The method of claim 19, wherein each representative image signal comprises a plurality of bits, and the serially outputting of the representative image signals comprises:

storing the read representative image signals in latch units; and

outputting, one bit at a time, the representative image signals stored in the latch units.

21. The method of claim 18, wherein the outputting of the representative image signals in synchronization with the second clock signal comprises:

generating the representative image signals that correspond to the respective display blocks;

storing the respective representative image signals in latch units; and

in synchronization with the second clock signal, performing bit-by-bit output of the representative image signals stored in the latch units.