ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE USING THE SAME
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Abstract
In an odd-shaped display whose display area is not rectangular in shape, a defect such as a reduction in the display quality due to the bright line or the like caused by the pixels that are located in a specific portion can be prevented. In an active matrix substrate used as a substrate of such an odd-shaped display in which the distribution area of the pixel electrodes corresponding to the display area has a shape other than rectangular, at least one dummy gate line is formed outside the gate line that is located at the outermost edge on the scanning start side. For peripheral pixels connected to the gate line and the gate line that lies on the scanning end side of the gate line, the gate lines located one row above the respective gate lines are extended on the opposite side of each of the peripheral pixels from the gate line to which the TFT of each of the peripheral pixels is connected. It is preferable that dummy pixels are located on the upper side of the individual peripheral pixels.
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Citations
22 Claims
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1-11. -11. (canceled)
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12. An active matrix substrate comprising:
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a plurality of gate lines to which scanning signals are applied; a plurality of source lines to which data signals are applied, the source lines being disposed at right angles to the gate lines; switching elements that are located in the vicinity of individual intersections of the gate lines and the source lines where each of the switching elements is connected to both the gate line and the source line; and pixel electrodes that are connected to the switching elements;
whereina distribution area of the pixel electrodes corresponding to a display area of the display device has a shape other than rectangular; at least one dummy gate line is located outside the gate line that is located at an outermost edge on a scanning start side of the gate lines in the distribution area; and among peripheral pixels located on a perimeter of the distribution area, when the gate line that is located at an outermost edge on the scanning start side of the gate lines is identified as a first gate line, the peripheral pixel connected to the nth gate line, where n is an integer of 2 or more, is interposed between the nth gate line and the (n−
1)th gate line that is extended on an opposite side of the peripheral pixel from the gate line to which the switching element of the peripheral pixel is connected. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification