IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME

• US 20090102994A1
• Filed: 10/08/2008
• Published: 04/23/2009
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Min-Jic, Oh, Jae-Young, Jin, Hyun-Cheol, Lee, Joon-Youp
• Granted Patent: US 8,319,903 B2
• Time in Patent Office: Days
• US Class Current: 349/38
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

An in-plane switching mode liquid crystal display according to an embodiment includes gate lines arranged in a first direction on an array substrate, data lines arranged in a second direction substantially perpendicular to the first direction, one or more storage electrodes provided on the array substrate, common electrodes extending across each pixel region, pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region, thin film transistors (TFTs) provided at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode, and at least one common line located under the respective common electrode in the pixel region, the common line being substantially parallel to the data lines.

Claims

1. An in-plane switching (IPS) mode liquid crystal display (LCD), comprising:

gate lines arranged in a first direction on an array substrate;

data lines arranged in a second direction substantially perpendicular to the first direction, the gate lines and the data lines defining pixel regions on the array substrate;

one or more storage electrodes provided on the array substrate;

common electrodes extending across each pixel region;

pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region;

thin film transistors (TFTs) provided at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode; and

at least one common line located under the respective common electrode in the pixel region, the common line being substantially parallel to the data lines.

2. The IPS mode LCD of claim 1, wherein the common line and the data line are made of the same conductive material and the common line is provided on the layer on which the data lines are formed.

3. The IPS mode LCD of claim 1, wherein the common line traverses the corresponding gate line with an insulating layer interposed between the common line and the gate line to prevent the corresponding gate line from short-circuiting with the common line.

4. The IPS mode LCD of claim 1, wherein a length of the common line extending across an entire region of the IPS mode LCD is shorter than a length of at least one of the gate lines extending across the entire region of the IPS mode LCD.

5. The IPS mode LCD of claim 1, wherein the common electrodes and the pixel electrodes are bent or curved at one or more portions.

6. The IPS mode LCD of claim 1, wherein a first connection line is connected with the common electrodes, the first connection line being substantially parallel to the gate lines.

7. The IPS mode LCD of claim 6, wherein a second connection line is connected with the pixel electrodes, the second connection line being electrically connected with the drain electrode and the storage electrodes.

8. The IPS mode LCD of claim 7, wherein the second connection line is electrically connected with the drain electrode and the storage electrodes via a first contact hole and second contact holes, respectively.

9. The IPS mode LCD of claim 7, wherein at least one of the common electrodes, the pixel electrodes, the first connection line and the second connection line is made of a transparent conductive material.

10. The IPS mode LCD of claim 1, wherein the common electrodes includes outermost common electrodes provided at edges of each pixel region.

11. The IPS mode LCD of claim 10, wherein the outermost common electrodes overlap with storage electrodes to form storage capacitors with first and second insulating layers interposed between the outermost common electrodes and the storage electrodes.

12. The IPS mode LCD of claim 6, wherein the common line is electrically connected with the first connection line via a third contact hole provided at a second insulating layer to supply a common voltage to the first connection line and the common electrodes.

13. The IPS mode LCD of claim 1, wherein the at least one common line includes first and second common lines provided under the respective common electrodes in the corresponding pixel region, the first and second common lines being substantially parallel to the data lines.

14. The IPS mode LCD of claim 1, wherein the one or more storage electrodes constitute a single storage electrode provided at one edge portion of a pixel area to form a single storage capacitor.

15. A method for fabricating an in-plane switching (IPS) type liquid crystal display (LCD) device, comprising:

forming gate lines arranged in a first direction and data lines arranged in a second direction substantially perpendicular to the first direction, the gate lines and the data lines defining pixel regions on an array substrate;

forming a storage electrode on the array substrate;

forming common electrodes extending across each pixel region;

forming pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region;

forming thin film transistors (TFTs) at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode; and

forming a common line under one of the common electrodes in the pixel region, the common line being substantially parallel to the data lines.

16. The method of claim 15, wherein the gate lines, the storage electrode, and a gate pad line are formed by depositing a first conductive film on a surface of the array substrate and selectively patterning the first conductive film through a first photolithography process.

17. The method of claim 15, wherein the source and drain electrodes, the common line, the data line and a data pad line are formed by forming a first insulating layer, an amorphous silicon thin film, an n+ amorphous silicon thin film, and a second conductive film on a surface of the array substrate with the gate electrode, the gate line, the storage electrode and a gate pad line formed thereon, and then selectively removing the amorphous silicon thin film, the n+ amorphous silicon thin film, and the second conductive film through a second photolithography process.

18. The method of claim 15, wherein a plurality of contact holes exposing portions of the drain electrode, the storage electrode, the common line, a data pad line and a gate pad line are formed by forming a second insulating layer on a surface of the array substrate with an active pattern, the source and drain electrodes, the data line, a data pad line and the common line formed thereon, and then selectively removing the second insulating layer through a third photolithography process.

19. The method of claim 15, wherein the common electrodes, the pixel electrodes, a first and second connection lines, a data pad electrode and a gate pad electrode are formed on a second insulating layer by forming a third conductive film made of a transparent conductive film on a surface of the array substrate with first to fifth contact holes formed thereon, and then selectively removing the third conductive film through a fourth photolithography process.

20. A method for fabricating an IPS mode LCD, comprising:

forming a gate electrode and a gate line on a first substrate;

forming a first insulating layer on the first substrate;

forming an active pattern on the first substrate;

forming source and drain electrodes on the first substrate and forming an data line crossing the gate line to define a pixel area;

forming a storage electrode on the first substrate;

forming at least one common line in a direction substantially parallel to the data line with in the pixel area of the first substrate;

forming a second insulating layer on the first substrate; and

forming a plurality of common electrodes and pixel electrodes alternately disposed within the pixel area of the firs substrate to generate an in-plane field, such that at least one common electrode is positioned at an upper portion of the common line.

21. The method of claim 20, further comprising:

forming a first connection line such that the first connection line is arranged to be substantially parallel to the gate line and connects one side of the common electrodes; and

forming a second connection line such that the second connection line is arranged to be substantially parallel to the gate line and connects one side of the pixel electrodes.

22. The method of claim 21, wherein the second connection line is electrically connected with the drain electrode via a first contact hole and electrically connected with the storage electrode via a second contact hole.

23. The method of claim 20, wherein the gate electrode, the gate line and the storage electrode are formed of a first conductive film, and

wherein the source and drain electrodes, the data line and the common line are formed of a second conductive film.

24. The method of claim 20, wherein the storage electrode is formed at an edge of pixel area of the first substrate in a direction substantially parallel to the data line, and overlapping with the common electrode with the first and second insulating layers interposed therebetween to form a storage capacitor.