INTEGRATED CIRCUIT MEMORY HAVING DYNAMICALLY ADJUSTABLE READ MARGIN AND METHOD THEREFOR

• US 20090103379A1
• Filed: 10/22/2007
• Published: 04/23/2009
• Est. Priority Date: 10/22/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Xu, Zheng, Zhang, Shayan, Snyder, Michael D., Ramamurthy, Hema
• Granted Patent: US 7,688,656 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.

Claims

1. A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, the method comprising:

setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value; and

if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is higher than the first value.

2. The method of claim 1, wherein the first value of the sense amplifier differential margin corresponds to a first selected operating point.

3. The method of claim 2, wherein the first selected operating point corresponds to a selected voltage and a selected frequency for operating the integrated circuit.

4. The method of claim 1, wherein the set of plurality of addressable units includes only one addressable unit that has incurred a higher failure rate than any of the remaining plurality of addressable units.

5. The method of claim 1, wherein the memory further comprises a plurality of sense amplifiers coupled to the plurality of addressable units, and wherein setting the sense amplifier differential margin comprises setting a sense amplifier enable assert time of the plurality of sense amplifiers.

6. The method of claim 4 further comprising incrementally setting the sense amplifier differential margin to a higher value than a previous value until a read operation on the addressable unit that has incurred the higher failure rate than any of the remaining plurality of addressable units does not result in a read data error.

7. The method of claim 1 further comprising decrementally setting the sense amplifier differential margin to a set of values starting from a highest possible value of the sense amplifier differential margin to a lowest value of the sense amplifier differential margin and incorporating an analysis of read errors resulting from setting of the sense amplifier differential margin to the set of values in a process of sorting the plurality of integrated circuits into bins based on the read errors.

8. A method for dynamically controlling sense amplifier differential margin of a memory, in an integrated circuit, comprising a plurality of addressable units, the plurality of addressable units comprising at least one failure prediction addressable unit, wherein the failure prediction addressable unit is configured to fail before the remaining plurality of addressable units, the method comprising:

setting the sense amplifier differential margin corresponding to the plurality of addressable units and the at least one failure prediction addressable unit to a first value; and

if a read data error occurs when data is read from the failure prediction addressable unit, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.

9. The method of claim 8, wherein the first value of the sense amplifier differential margin corresponds to a first selected operating point.

10. The method of claim 9, wherein the first selected operating point corresponds to a selected voltage and a selected frequency for operating the integrated circuit.

11. The method of claim 8, wherein the memory further comprises a plurality of sense amplifiers coupled to the plurality of addressable units, and wherein setting the sense amplifier differential margin comprises setting a sense amplifier enable assert time of the plurality of sense amplifiers.

12. The method of claim 8 further comprising incrementally setting the sense amplifier differential margin to a higher value than a previous value until a read operation on the failure prediction addressable unit does not result in a read data error.

13. A method for dynamically controlling sense amplifier differential margin of a memory, in an integrated circuit, comprising a plurality of addressable units and at least one redundant addressable unit, the method comprising:

setting the sense amplifier differential margin corresponding to the plurality of addressable units and the at least one redundant addressable unit to a first value; and

if a read data error occurs when data is read from any one of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units and the at least one redundant addressable unit to a second value, wherein the second value is greater than the first value;

incrementally increasing the sense amplifier differential margin to a maximum value if a read data error continues to occur for any one of the plurality of addressable units; and

substituting the redundant addressable unit in place of a defective addressable unit, wherein the defective addressable unit is one of the plurality of addressable units that generates a read data error even when the sense amplifier differential margin is set to the maximum value.

14. The method of claim 13, wherein the first value of the sense amplifier differential margin corresponds to a first selected operating point.

15. The method of claim 14, wherein the first selected operating point corresponds to a selected voltage and a selected frequency for operating the integrated circuit.

16. The method of claim 13, wherein the memory further comprises a plurality of sense amplifiers coupled to the plurality of addressable units and the redundant addressable unit, and wherein setting the sense amplifier differential margin comprises setting a sense amplifier enable assert time of the plurality of sense amplifiers and the redundant addressable unit.

17. An integrated circuit comprising a memory, wherein the memory comprises a plurality of addressable units, the memory further comprising:

a memory array coupled to a plurality of sense amplifiers; and

a feedback path configured for;

setting a sense amplifier differential margin for the plurality of sense amplifiers to a first value,

detecting a read data error when data is read from at least one of the plurality of addressable units, and

setting the sense amplifier differential margin for the plurality of addressable units to a second value, wherein the second value is greater than the first value.

18. The integrated circuit of claim 17, wherein the first value of the sense amplifier differential margin corresponds to a first selected operating point.

19. The integrated circuit of claim 17, wherein the first selected operating point corresponds to a selected voltage and a selected frequency for operating the integrated circuit.

20. The integrated circuit of claim 17, wherein the feedback path comprises an error detector for detecting the read data error.

21. The integrated circuit of claim 17, wherein the feedback path is further configured for incrementally setting the sense amplifier differential margin to a higher value than a previous value until a read operation on an addressable unit that has incurred a higher failure rate than any of the remaining plurality of addressable units does not result in a read data error.