SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND

• US 20090103380A1
• Filed: 10/17/2007
• Published: 04/23/2009
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: TSAI, VICTOR Y., PEKNY, THEODORE T., FEELEY, PETER S.
• Granted Patent: US 8,103,936 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Claims

1. A memory device, comprising:

a serial peripheral interface NAND controller adapted to receive an activate signal, a timing signal, and a serial data in signal, wherein the serial peripheral interface NAND controller is further adapted to transmit the serial in data signal without translation into standard NAND format; and

a NAND memory adapted to receive the serial data in signal transmitted from the serial peripheral interface NAND controller.

2. The memory device of claim 1, comprising a cache memory coupled to the serial peripheral interface NAND controller and the NAND memory, wherein the cache memory is adapted to transmit data from the serial peripheral interface NAND controller to the NAND memory, and wherein the cache memory is further adapted to transmit data from the NAND memory to the serial peripheral interface NAND controller.

3. The memory device of claim 1, comprising an error correction status register coupled to the serial peripheral interface NAND controller.

4. The memory device of claim 1, wherein the serial peripheral interface NAND controller is adapted to perform error correction on data stored in the cache memory.

5. The memory device of claim 4, wherein performing error correction on data stored in the cache memory comprises:

reading data in the cache memory;

detecting errors in the data; and

updating an error correction status register.

6. The memory device of claim 4, wherein performing error correction on data stored in the cache memory comprises:

reading data in the cache memory;

detecting errors in the data;

correcting at least one error in the data; and

updating an error correction status register.

7. The memory device of claim 3, wherein the error correction status register is adapted to store error types for the cache.

8. The memory device of claim 3, wherein the error correction status register is adapted to store error correction enable and disable information.

9. The memory device of claim 3, wherein the error correction status register is adapted to store information defining the size of the region on which the ECC algorithm is to be performed.

10. A method for accessing a serial peripheral interface NAND memory device, comprising:

setting a chip select to low in a host device;

transmitting a page read command to the serial peripheral interface NAND memory device;

transmitting a page address to the serial peripheral interface NAND memory device, wherein the page address is sent to a NAND memory in the serial peripheral interface NAND memory device without translation of the page address into standard NAND format; and

setting a chip select to high in the host device.

11. The method of claim 10, further comprising:

setting the chip select to low in the host device;

transmitting a read status command to the serial peripheral interface NAND memory device; and

receiving a read status bit from the serial peripheral interface NAND memory device.

12. The method of claim 11, further comprising:

transmitting a data read command to the serial peripheral interface NAND memory device;

transmitting a data address to the serial peripheral interface NAND memory device; and

receiving data from the serial peripheral interface NAND memory device.

13. The method of claim 12, wherein receiving data comprises receiving data that has been checked by an error correction process.

14. The method of claim 10, further comprising:

waiting a predetermined time;

setting the chip select to low in the host device;

transmitting a data read command to the serial peripheral interface NAND memory device;

transmitting a data address to the serial peripheral interface NAND memory device; and

receiving data from the serial peripheral interface NAND memory device.

15. The method of claim 14, wherein receiving data comprises receiving data that has been checked by an error correction process.

16. A method of operating a serial peripheral interface NAND memory device, comprising:

providing a timing signal comprising a plurality of clock cycles;

providing an activate signal; and

providing a serial data in signal, wherein the data transmitted across the serial data in signal is input to NAND memory in a modified serial peripheral interface NAND format.

17. The method of claim 16, further comprising receiving a serial data out signal, wherein receiving the serial data out signal comprises receiving data output from the NAND memory in the modified serial peripheral interface format.

18. The method of claim 16, further comprising receiving data output from the NAND memory that has been checked by an error correction process.

19. A method for accessing a serial peripheral interface NAND memory device, comprising:

transmitting a page read command to the serial peripheral interface NAND memory device;

transmitting a page address to the serial peripheral interface NAND memory device, wherein the page address is sent to a NAND memory in the serial peripheral interface NAND memory device in a modified serial peripheral interface NAND format;

transmitting a data page associated with the page address to a cache memory from the NAND memory;

performing an error detection and correction algorithm on the data page stored in the cache memory;

transmitting a data read command to the serial peripheral interface NAND memory device;

transmitting a data address to the serial peripheral interface NAND memory device; and

receiving data from the serial peripheral interface NAND memory device.

20. The method of claim 19, wherein performing the error detection and correction algorithm comprises using a linear block code to detect and correct errors in the data.

21. The method of claim 19, wherein the error detection and correction algorithm comprises using a BCH code, a Hamming code, or a Reed-Solomon code.

22. The method of claim 19, wherein performing the error detection and correction algorithm includes updating an ECC NAND memory result register.

23. A method for accessing a serial peripheral interface NAND memory device, comprising:

transmitting a page read command to the serial peripheral interface NAND memory device;

transmitting a page address to the serial peripheral interface NAND memory device, wherein the page address is sent to a NAND memory in the NAND memory device in a modified serial peripheral interface NAND format;

transmitting a data page associated with the page address to a cache memory from the NAND memory device;

performing an error detection and correction algorithm on the data page stored in the cache memory;

transmitting a data read command to the serial peripheral interface NAND memory device;

transmitting a data address to the serial peripheral interface NAND memory device; and

receiving data from the serial peripheral interface NAND memory device.

24. The method of claim 23, wherein performing the error detection and correction algorithm comprises using a BCH code, a Hamming code, or a Reed-Solomon code.

25. The method of claim 23, wherein performing the error detection and correction algorithm includes updating an ECC NAND memory result register.