SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND
First Claim
1. A memory device, comprising:
- a serial peripheral interface NAND controller adapted to receive an activate signal, a timing signal, and a serial data in signal, wherein the serial peripheral interface NAND controller is further adapted to transmit the serial in data signal without translation into standard NAND format; and
a NAND memory adapted to receive the serial data in signal transmitted from the serial peripheral interface NAND controller.
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Accused Products
Abstract
A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
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Citations
25 Claims
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1. A memory device, comprising:
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a serial peripheral interface NAND controller adapted to receive an activate signal, a timing signal, and a serial data in signal, wherein the serial peripheral interface NAND controller is further adapted to transmit the serial in data signal without translation into standard NAND format; and a NAND memory adapted to receive the serial data in signal transmitted from the serial peripheral interface NAND controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for accessing a serial peripheral interface NAND memory device, comprising:
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setting a chip select to low in a host device; transmitting a page read command to the serial peripheral interface NAND memory device; transmitting a page address to the serial peripheral interface NAND memory device, wherein the page address is sent to a NAND memory in the serial peripheral interface NAND memory device without translation of the page address into standard NAND format; and setting a chip select to high in the host device. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method of operating a serial peripheral interface NAND memory device, comprising:
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providing a timing signal comprising a plurality of clock cycles; providing an activate signal; and providing a serial data in signal, wherein the data transmitted across the serial data in signal is input to NAND memory in a modified serial peripheral interface NAND format. - View Dependent Claims (17, 18)
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19. A method for accessing a serial peripheral interface NAND memory device, comprising:
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transmitting a page read command to the serial peripheral interface NAND memory device; transmitting a page address to the serial peripheral interface NAND memory device, wherein the page address is sent to a NAND memory in the serial peripheral interface NAND memory device in a modified serial peripheral interface NAND format; transmitting a data page associated with the page address to a cache memory from the NAND memory; performing an error detection and correction algorithm on the data page stored in the cache memory; transmitting a data read command to the serial peripheral interface NAND memory device; transmitting a data address to the serial peripheral interface NAND memory device; and receiving data from the serial peripheral interface NAND memory device. - View Dependent Claims (20, 21, 22)
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23. A method for accessing a serial peripheral interface NAND memory device, comprising:
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transmitting a page read command to the serial peripheral interface NAND memory device; transmitting a page address to the serial peripheral interface NAND memory device, wherein the page address is sent to a NAND memory in the NAND memory device in a modified serial peripheral interface NAND format; transmitting a data page associated with the page address to a cache memory from the NAND memory device; performing an error detection and correction algorithm on the data page stored in the cache memory; transmitting a data read command to the serial peripheral interface NAND memory device; transmitting a data address to the serial peripheral interface NAND memory device; and receiving data from the serial peripheral interface NAND memory device. - View Dependent Claims (24, 25)
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Specification