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SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND

  • US 20090103380A1
  • Filed: 10/17/2007
  • Published: 04/23/2009
  • Est. Priority Date: 10/17/2007
  • Status: Active Grant
First Claim
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1. A memory device, comprising:

  • a serial peripheral interface NAND controller adapted to receive an activate signal, a timing signal, and a serial data in signal, wherein the serial peripheral interface NAND controller is further adapted to transmit the serial in data signal without translation into standard NAND format; and

    a NAND memory adapted to receive the serial data in signal transmitted from the serial peripheral interface NAND controller.

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