Digital Video Broadcast Service Discovery

• US 20090103651A1
• Filed: 10/18/2007
• Published: 04/23/2009
• Est. Priority Date: 10/18/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Nokia Corporation
• Inventors: Vesma, Jussi, Tupala, Miika, Lahtonen, Jyrki
• Granted Patent: US 8,045,628 B2
• Time in Patent Office: Days
• US Class Current: 375/308
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself
• CPC Class Codes: H04L 27/2613 Structure of the reference signals
• CPC Class Codes: H04L 27/2659 Coarse or integer frequency offset determination and synchronisation
• CPC Class Codes: H04L 27/2675 Pilot or known symbols
• CPC Class Codes: H04L 27/2685 Speed of convergence
• CPC Class Codes: H04L 5/0007 the frequencies being orthogonal, e.g. OFDM(A), DMT
• CPC Class Codes: H04L 5/005 of common pilots, i.e. pilots destined for multiple users or terminals
• CPC Class Codes: H04L 5/0053 Allocation of signaling, i.e. of overhead other than pilot signals

Abstract

Embodiments are directed to binary phase shift key modulating a first pilot symbol according to a reference sequence, and differentially binary phase shift key modulating a second pilot symbols. The original reference sequence and the delayed differentially modulated sequence are then combined before performing an Inverse Fast Fourier Transform and inserting a guard interval. Receiver operations are an inverse of the transmitter operations, which were just discussed. The receiver does not have to know the reference sequence. Embodiments are directed to specifying a plurality of seeds that are bit patterns each having r bits not all of which have a value of zero, extending the seeds into respective sequences by applying to each seed a recurrence formula; and using one of the sequences as a comb sequence and using the sequences other than the comb sequence as binary phase shift keying patterns.

Claims

1. A method comprising:

binary phase shift key modulating a first pilot symbol according to a reference sequence;

differentially modulating a second pilot symbol to generate a differentially modulated sequence;

generating a combined modulated signal by combining the original reference sequence and the differentially modulated sequence; and

performing an inverse fast Fourier transform on, and inserting a guard interval into, the combined modulated signal.

2. The method of claim 1, wherein the first pilot symbol is configured for use as a channel estimate.

3. The method of claim 2, wherein the channel estimate is configured for use in equalizing a second pilot symbol.

4. The method of claim 1, wherein the step of differentially modulating the second pilot symbol is performed according to at least one of the following rules:

if pseudo random binary sequence_k=0, then b_k,2=b_k,1 and if pseudo random binary sequence_k=1, then b_k,2=−

b_k,1, and

if pseudo random binary sequence_k=0, then b_k,2=−

b_k,1 and if pseudo random binary sequence_k=1, then b_k,2=b_k,1, where pseudo random binary sequence_k is the kth element of the pseudo random binary sequence, and b_k,m is the transmitted symbol on kth carrier at mth pilot symbol.

5. Apparatus comprising a processor and a memory containing executable instructions that, when executed by the processor, perform:

binary phase shift key modulating a first pilot symbol according to a reference sequence;

differentially modulating a second pilot symbol to generate a differentially modulated sequence;

generating a combined modulated signal by combining the original reference sequence and the differentially modulated sequence; and

performing an inverse fast Fourier transform on, and inserting a guard interval into, the combined modulated signal.

6. The apparatus of claim 5, wherein the first pilot symbol is configured for use as a channel estimate.

7. The apparatus of claim 5, wherein the channel estimate is configured for use in equalizing a second pilot symbol.

8. The apparatus of claim 5, wherein differentially modulating the second pilot symbol is performed according to at least one of the following rules:

if pseudo random binary sequence_k=0, then b_k,2=b_k,1 and if pseudo random binary sequence_k=1, then b_k,2=−

b_k,1, and

if pseudo random binary sequence_k=0, then b_k,2=−

b_k,1 and if pseudo random binary sequence_k=1, then b_k,2=b_k,1, where pseudo random binary sequence_k is the kth element of the pseudo random binary sequence, and b_k,m is the transmitted symbol on kth carrier at mth pilot symbol.

9. The apparatus of claim 5, wherein the first and second pilot symbols each use a 1 k fast Fourier Transform.

10. The apparatus of claim 5, wherein the first and second pilot symbols have a 1/1 guard interval.

11. A method comprising:

receiving a first pilot symbol and a second pilot symbol;

removing a guard interval from the first and second pilot symbols;

performing a fast fourier transform on the first and second pilot symbols; and

differentially demodulating the first and second pilot symbols to generate an estimated pseudo random binary sequence.

12. The method of claim 11, further comprising:

using the first pilot symbol as a channel estimate.

13. The method of claim 12, further comprising:

using the channel estimate to equalize the second pilot symbol.

14. The method of claim 11, wherein the step of differentially demodulating the first and second pilot symbols to generate an estimated pseudo random binary sequence is performed according to at least one of the following rules:

if b_k,2=b_k,1 then the estimated pseudo random binary sequence_k=0, and if b_k,2=−

b_k,1 then the estimated pseudo random binary sequence_k=1, and

if b_k,2=−

b_k,1 then the estimated pseudo random binary sequence_k=0, and if b_k,2=b_k,1, then the estimated pseudo random binary sequence_k=1, where the estimated pseudo random binary sequence_k is the kth element of the estimated pseudo random binary sequence, and b_k,m is the received symbol on kth carrier at mth pilot symbol.

15. Apparatus comprising a processor and a memory containing executable instructions that, when executed by the processor, perform:

receiving a first pilot symbol and a second pilot symbol;

removing a guard interval from the first and second pilot symbols;

performing a fast fourier transform on the first and second pilot symbols; and

differentially demodulating the first and second pilot symbols to generate an estimated pseudo random binary sequence.

16. The apparatus of claim 15, wherein the memory contains further executable instructions that, when executed by the processor, perform:

using the first pilot symbol as a channel estimate.

17. The apparatus of claim 16, wherein the memory contains further executable instructions that, when executed by the processor, perform:

using the channel estimate to equalize the second pilot symbol.

18. The apparatus of claim 15, wherein differentially demodulating the first and second pilot symbols to generate an estimated pseudo random binary sequence is performed according to at least one of the following rules:

if b_k,2=b_k,1, then the estimated pseudo random binary sequence_k=0, and if b_k,2=−

b_k,1 then the estimated pseudo random binary sequence_k=1, and

if b_k,2=−

b_k,1 then the estimated pseudo random binary sequence_k=0, and if b_k,2=b_k,1, then the estimated pseudo random binary sequence_k=1, where the estimated pseudo random binary sequence_k is the kth element of the estimated pseudo random binary sequence, and b_k,m is the received symbol on kth carrier at mth pilot symbol.

19. Apparatus comprising a processor and a memory containing executable instructions that, when executed by the processor, perform:

specifying a plurality of seeds that are bit patterns each having r bits not all of which have a value of zero;

extending the seeds into respective sequences of length 2^r−

1 by applying to each seed a recurrence formula determined by a primitive polynomial of degree r; and

using one of the sequences as a comb sequence and using the sequences other than the comb sequence as binary phase shift keying patterns by interpreting 0 and 1 values as +1 and −

1 values.

20. The apparatus of claim 19, wherein the primitive polynomial is 1+x⁴+x⁹.

21. The apparatus of claim 20, wherein the comb sequence is based on a seed having a value of 100 000 000.

22. The apparatus of claim 21, wherein additional seeds include at least one of:

000 110 101, 110 001 100, 101 111 101, 101 101 111, and 111 100 111 interpreted as values of plus 1 and minus 1, as opposed to 0 and 1.

23. The apparatus of claim 21, wherein the seeds are extended to sequences P, and S_m for m=1, 2, 3, 4 and 5 by repeated applications of the recurrence formulas P(k)=P(k−

4)+P(k−

9)(mod

     2), and S_m(k)=S_m(k−

4)*S_m(k−

9), for k=9, 10, . . . , 510.

24. The apparatus of claim 23, wherein the memory contains further executable instructions that, when executed by the processor, perform:

calculating pilot symbol signals as

25. The apparatus of claim 24, wherein n=±

37, ±

75, ±

112 correspond to frequency offsets of ±

1/6, ±

1/3, ±

1/2 MHz.