Linear phase interpolator and phase detector
First Claim
1. An interpolating phase detector array for comparing a phase of a reference clock signal with phases of a set of K phase shifted clock signals and generating a phase error output signal, the interpolating phase detector array comprising:
- a plurality of N phase detector columns, each column including;
a plurality of M exclusive-OR (XOR) blocks, each block having;
inputs for receiving the reference clock signal, receiving two of the phase shifted clock signals, receiving “
coarse”
control signals for enabling said received phase shifted clock signals; and
a phase error output;
a steerable current source having first and second current sink outputs for delivering a bias current to two distinct sets of XOR blocks, and having an input to receive a “
fine”
control signal for directing the bias current to one of said distinct sets; and
a current output IOUT for delivering the phase error output signal formed by joining phase error outputs of the XOR blocks.
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Abstract
A novel interpolating phase detector for use in a multiphase PLL is described comprising an array of individual phase comparators, all operating at essentially the same operating point which permits the circuits to be designed simultaneously for high speed and for low power consumption. Two adjacent phase outputs of a multi-phase VCO may be selected and interpolated in between, by selectively attaching a variable number of phase comparators to each phase output and summing their phase error outputs. By varying the number of phase comparators attached to each phase output, interpolation can be achieved with high linearity.
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Citations
25 Claims
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1. An interpolating phase detector array for comparing a phase of a reference clock signal with phases of a set of K phase shifted clock signals and generating a phase error output signal, the interpolating phase detector array comprising:
a plurality of N phase detector columns, each column including; a plurality of M exclusive-OR (XOR) blocks, each block having; inputs for receiving the reference clock signal, receiving two of the phase shifted clock signals, receiving “
coarse”
control signals for enabling said received phase shifted clock signals; anda phase error output; a steerable current source having first and second current sink outputs for delivering a bias current to two distinct sets of XOR blocks, and having an input to receive a “
fine”
control signal for directing the bias current to one of said distinct sets; anda current output IOUT for delivering the phase error output signal formed by joining phase error outputs of the XOR blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An interpolating phase detector array for comparing a phase of a reference clock signal with phases of a set of K phase shifted clock signals and generating a phase error output signal, the phase detector array comprising:
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a matrix of M rows by N columns of exclusive-OR (XOR) blocks, and a set of N steerable current sources; each of the XOR blocks including a reference clock input connected to the reference clock signal, further including first and second phase shifted clock inputs connected to selected ones of the set of phase shifted clock signals, a bias current input, and a phase error output, the phase error outputs of all XOR blocks being joined into a current output IOUT for delivering the phase error output signal; and each of the N steerable current sources being assigned to a distinct one of the columns of the XOR-blocks, each steerable current source including a first current sink output connected to the bias current inputs of the XOR-blocks of odd-numbered rows, and second current sink outputs connected to the bias current inputs of the XOR-blocks of even-numbered rows. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method for detecting a phase error in an interpolating phase detector array, including the steps of:
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providing an array of XOR blocks arranged in M rows and N columns for comparing a phase of a reference clock signal with phases of a set of K phase shifted clock signals; enabling a first subset of the XOR blocks in one of the M rows to perform the comparison with the phase of a first one of the K phase shifted clock signals, under control of a first “
coarse”
control signal;enabling a second subset of the XOR blocks in a different one of the M rows to perform the comparison with the phase of a second one of the K phase shifted clock signals, under control of a second “
coarse”
control signal, the phase of the second phase shifted clock signal differing from the phase of the first phase shifted clock signal by approximately 360/K degrees;providing each enabled XOR block with a bias current of unit strength; and generating a phase error output signal by combining comparison outputs from all enabled XOR blocks. - View Dependent Claims (15, 16, 17, 18)
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19. A phase lock loop (PLL) including a multiphase voltage controlled oscillator (VCO) generating a set of K phase shifted clock signals whose frequency is controlled through a frequency control input, and an interpolating phase detector array designed for comparing a phase of a reference clock signal with phases of the phase shifted clock signals and for generating a phase error output signal, the interpolating phase detector array comprising:
a plurality of N phase detector columns, each phase detector column including; a plurality of M exclusive-OR (XOR) blocks, each having inputs for receiving the reference clock signal, receiving two of the phase shifted clock signals, receiving “
coarse”
control signals for enabling said received phase shifted clock signals, and having a phase error output; anda steerable current source having first and second current sink outputs for delivering a bias current to two distinct sets of XOR blocks, and having an input to receive a “
fine”
control signal for directing the bias current to one of said distinct sets; andthe phase error outputs of all XOR blocks being joined into a current output IOUT for delivering the phase error output signal. - View Dependent Claims (20, 21, 22, 23, 24, 25)
Specification