VERTICAL GATED ACCESS TRANSISTOR
First Claim
1. A method of forming an apparatus, the method comprising:
- forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate, wherein at least one of the shallow trenches is positioned between two deep trenches, and wherein the plurality of shallow trenches and the plurality of deep trenches are parallel to each other;
depositing a layer of conductive material over the first region and a second region of the substrate;
etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate;
masking the second region of the substrate;
removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed; and
etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked, wherein the elongate trenches have an intermediate depth between depths of the deep trenches and the shallow trenches.
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Accused Products
Abstract
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.
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Citations
71 Claims
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1. A method of forming an apparatus, the method comprising:
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forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate, wherein at least one of the shallow trenches is positioned between two deep trenches, and wherein the plurality of shallow trenches and the plurality of deep trenches are parallel to each other; depositing a layer of conductive material over the first region and a second region of the substrate; etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate; masking the second region of the substrate; removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed; and etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked, wherein the elongate trenches have an intermediate depth between depths of the deep trenches and the shallow trenches. - View Dependent Claims (2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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3. (canceled)
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23-52. -52. (canceled)
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53. A method comprising:
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patterning a plurality of shallow trenches and a plurality of deep trenches in a substrate array region; patterning a plurality of intermediate-depth trenches in the substrate array region, wherein the intermediate-depth trenches cross the shallow and deep trenches, wherein the intermediate-depth, shallow and deep trenches define a plurality of U-shaped transistor structures in the substrate array region, and wherein the plurality of intermediate-depth trenches are defined by a photolithography mask; forming a plurality of gate electrode sidewall spacers in the intermediate-depth trenches; and patterning a plurality of planar transistor structures in a substrate logic region, wherein the plurality of planar transistor structures are defined by the photolithography mask. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 68, 69, 70, 71)
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67. (canceled)
Specification