METHOD TO IMPROVE ELECTRICAL LEAKAGE PERFORMANCE AND TO MINIMIZE ELECTROMIGRATION IN SEMICONDUCTOR DEVICES
First Claim
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1. A method of minimizing electromigration in conductive paths and gettering metal contaminants in dielectric regions of a workpiece, the method comprising:
- planarizing a top surface of a workpiece to form a substantially planar surface with a plurality of conductive paths and a plurality of dielectric regions;
exposing the top surface of the workpiece to one or more gas cluster ion beams (GCIB) using a material source comprising one or more elements selected from the group consisting of B, C, Si, Ge, N, P, As, O, S, and Cl, to form a doped layer in the plurality of conductive paths and the plurality of dielectric regions; and
forming a barrier layer over the doped layer.
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Abstract
Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.
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Citations
21 Claims
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1. A method of minimizing electromigration in conductive paths and gettering metal contaminants in dielectric regions of a workpiece, the method comprising:
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planarizing a top surface of a workpiece to form a substantially planar surface with a plurality of conductive paths and a plurality of dielectric regions; exposing the top surface of the workpiece to one or more gas cluster ion beams (GCIB) using a material source comprising one or more elements selected from the group consisting of B, C, Si, Ge, N, P, As, O, S, and Cl, to form a doped layer in the plurality of conductive paths and the plurality of dielectric regions; and forming a barrier layer over the doped layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming a doped layer, the method comprising:
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planarizing a top surface of a workpiece to form a substantially planar surface with a plurality of conductive paths and a plurality of dielectric regions; infusing material into the top surface of the workpiece using a GCIB to form a doped layer in the plurality of conductive paths and the plurality of dielectric regions, wherein the material comprises one or more elements selected from the group consisting of B, C, Si, Ge, N, P, As, O, S, and Cl; and forming a barrier layer over the doped layer. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method of incorporating one or more elements in a device structure, the method comprising:
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planarizing a top surface of a workpiece to create a substantially planar surface comprising a plurality of conductive paths and a plurality of dielectric regions; depositing a barrier layer over the substantially planar surface thereby forming an interface between the substantially planar surface and the barrier layer; and doping at least a portion of the barrier layer adjacent the interface using a GCIB to introduce one or more elements selected from the group consisting of B, C, Si, Ge, N, P, As, O, S, and Cl to form a doped barrier layer and to provide the dopant at least at the interface between the substantially planar surface and the barrier layer.
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18. A method of minimizing electromigration in conductive paths on a workpiece, the method comprising:
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forming one or more conductive paths on a workpiece; and exposing the top surface of the workpiece to a phosphorous source to form a phosphorous-doped layer in the one or more conductive paths. - View Dependent Claims (19, 20, 21)
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Specification