READING ANALOG MEMORY CELLS USING BUILT-IN MULTI-THRESHOLD COMMANDS

• US 20090106485A1
• Filed: 07/23/2008
• Published: 04/23/2009
• Est. Priority Date: 10/19/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Anholt, Micha
• Granted Patent: US 8,068,360 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command.

Claims

1. A method for data storage, comprising:

storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; and

after storing the data, reading the first data bits from the memory cells by executing at least the second built-in command.

2. The method according to claim 1, wherein reading the first data bits by executing at least the second built-in command comprises reading multiple instances of the first data bits using the respective second thresholds.

3. The method according to claim 2, and comprising processing the multiple instances of the first data bits so as to adjust the first thresholds.

4. The method according to claim 2, and comprising processing the multiple instances of the first data bits so as to cancel interference in the analog memory cells.

5. The method according to claim 2, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), and comprising processing the multiple instances of the first data bits so as to compute soft decoding metrics for decoding the ECC.

6. The method according to claim 1, wherein reading the first data bits by executing at least the second built-in command comprises making an attempt to read the first data bits using the first built-in command, and reverting to read the first data bits using the second built-in command responsively to a failure of the attempt.

7. The method according to claim 1, wherein each of the analog memory cells further stores a third data bit, wherein the memory has a third built-in command for reading the third data bits of the memory cells by comparing the storage values of the memory cells to a third number of third thresholds, such that the third number is larger than the second number, and wherein reading the first data bits comprises executing both the second and the third built-in commands.

8. The method according to claim 1, wherein storing the data comprises writing to the memory cells nominal storage values selected from a group of possible nominal storage values corresponding to the respective programming levels, and wherein executing at least the second built-in command comprises positioning the second thresholds between a pair of the nominal storage values that are adjacent to one another in the group of the possible nominal storage values.

9. The method according to claim 1, wherein the storage values of the memory cells that assume a given programming level are distributed over a range, and wherein executing at least the second built-in command comprises positioning at least one of the second thresholds within the range.

10. The method according to claim 1, wherein the second built-in command reads the second data bits independently of the first data bits.

11. A method for data storage, comprising:

storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; and

after storing the data, reading the first data bits from the memory cells by executing at least the second built-in command.

12. Apparatus for data storage, comprising:

an interface, which is operative to communicate with a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.

13. The apparatus according to claim 12, wherein the processor is coupled to read multiple instances of the first data bits using the respective second thresholds by executing at least the second built-in command comprises.

14. The apparatus according to claim 13, wherein the processor is coupled to process the multiple instances of the first data bits so as to adjust the first thresholds.

15. The apparatus according to claim 13, wherein the processor is coupled to process the multiple instances of the first data bits so as to cancel interference in the analog memory cells.

16. The apparatus according to claim 13, wherein the processor is coupled to encode the stored data with an Error Correction Code (ECC), and to process the multiple instances of the first data bits so as to compute soft decoding metrics for decoding the ECC.

17. The apparatus according to claim 12, wherein the processor is coupled to make an attempt to read the first data bits using the first built-in command, and to revert to read the first data bits using the second built-in command responsively to a failure of the attempt.

18. The apparatus according to claim 12, wherein each of the analog memory cells further stores a third data bit, wherein the memory has a third built-in command for reading the third data bits of the memory cells by comparing the storage values of the memory cells to a third number of third thresholds, such that the third number is larger than the second number, and wherein the processor is coupled to read the first data bits by executing both the second and the third built-in commands.

19. The apparatus according to claim 12, wherein the processor is coupled to store the data by writing to the memory cells nominal storage values selected from a group of possible nominal storage values corresponding to the respective programming levels, and to position the second thresholds, which are used in executing the second built-in command, between a pair of the nominal storage values that are adjacent to one another in the group of the possible nominal storage values.

20. The apparatus according to claim 12, wherein the storage values of the memory cells that assume a given programming level are distributed over a range, and wherein the processor is coupled to position at least one of the second thresholds, which are used in executing the second built-in command, within the range.

21. The apparatus according to claim 12, wherein the second built-in command reads the second data bits independently of the first data bits.

22. Apparatus for data storage, comprising:

a memory comprising multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.

23. Apparatus for data storage, comprising:

an interface, which is operative to communicate with a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.

24. Apparatus for data storage, comprising:

a memory comprising multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values, the memory having at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to one or more first thresholds, and a second built-in command for reading the second data bits of the memory cells independently of the first data bits by comparing the storage values of the memory cells to a plurality of second thresholds; and

a processor, which is coupled to store data in the memory cells and, after storing the data, to read the first data bits from the memory cells by executing at least the second built-in command.