ALLOCATING SPACE IN DEDICATED CACHE WAYS

• US 20090106494A1
• Filed: 10/19/2007
• Published: 04/23/2009
• Est. Priority Date: 10/19/2007
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: KNEBEL, Patrick
• Granted Patent: US 8,176,255 B2
• Time in Patent Office: Days
• US Class Current: 711/119
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1021 Hit rate improvement

Abstract

A system comprises a processor core and a cache coupled to the core and comprising at least one cache way dedicated to the core, where the cache way comprises multiple cache lines. The system also comprises a cache controller coupled to the cache. Upon receiving a data request from the core, the cache controller determines whether the cache has a predetermined amount of invalid cache lines. If the cache does not have the predetermined amount of invalid cache lines, the cache controller is adapted to allocate space in the cache for new data, where the space is allocable in the at least one cache way dedicated to the core.

Claims

1. A system, comprising:

a processor core;

a cache coupled to the core and comprising at least one cache way dedicated to the core, said cache way comprising multiple cache lines; and

a cache controller coupled to the cache;

wherein, upon receiving a data request from the core, the cache controller determines whether said cache has a predetermined amount of invalid cache lines;

wherein, if the cache does not have said predetermined amount of invalid cache lines, the cache controller is adapted to allocate space in the cache for new data, the space allocable in said at least one cache way dedicated to the core.

2. The system of claim 1, wherein the processor core provides an identification signal to the cache controller, and wherein the cache controller uses said identification signal to determine in which of a plurality of cache ways said space should be allocated.

3. The system of claim 1, wherein the system further comprises another processor core, and wherein said cache comprises a different cache way dedicated to said another processor core, and wherein the cache controller allocates additional space in the different cache way in response to another data request from said another processor core.

4. The system of claim 1, wherein, if the cache has said predetermined amount of invalid cache lines, the cache controller evicts an invalid cache line and replaces the evicted, invalid cache line with said new data.

5. The system of claim 1, wherein said predetermined amount of invalid cache lines comprises one invalid cache line.

6. The system of claim 1, wherein the cache controller allocates said space using either a Not Recently Used (NRU) or Least Recently Used (LRU) replacement algorithm.

7. The system of claim 1, wherein, if the cache does not have said predetermined amount of invalid cache lines, the cache controller is configured to search multiple ways in the cache for a line associated with a hint bit that indicates that the line is not associated with another line stored in a different cache, said different cache of a higher-level than said cache.

8. The system of claim 1, wherein the system comprises a computer.

9. A system, comprising:

a first processor core associated with a first cache;

a second processor core associated with a second cache;

a third cache associated with both the first and second processor cores, said third cache comprises multiple ways, a different one of said multiple ways dedicated to each of the processor cores; and

a cache controller coupled to the first, second and third caches;

wherein, if a cache miss is generated in the first cache, and if there do not exist a predetermined number of invalid lines in said third cache, the cache controller searches each of multiple ways of the third cache for a line that indicates that the line is not stored in the first or second caches;

wherein, if said line is found, the cache controller allocates space in a target way of the third cache associated with the line and stores data in said target way.

10. The system of claim 9, wherein, if said line is not found, the cache controller obtains identification associated with said first processor core and uses said identification to identify the different one of said multiple ways dedicated to the first processor core;

and

wherein the third cache stores said data in said different one of said multiple ways dedicated to the first processor core.

11. The system of claim 10, wherein the third cache stores said data in said different one of said multiple ways dedicated to the first processor core using either a Not Recently Used (NRU) or Least Recently Used (LRU) replacement algorithm.

12. The system of claim 9, wherein the third cache comprises all information stored in the first and second caches.

13. The system of claim 9, wherein the system comprises a computer.

14. The system of claim 9, wherein, if a different line is evicted from said first cache or from said second cache, the cache controller locates another line in the third cache that corresponds to the different line, and wherein the cache controller adjusts a hint bit associated with the another line, said hint bit indicates whether the different line is stored in the first cache or the second cache.

15. The system of claim 9, wherein said predetermined number is one.

16. A method, comprising:

generating a request for data;

determining whether a cache comprises said data, said cache comprising multiple ways;

if said cache does not comprise said data and there are not a predetermined number of invalid lines in said cache, searching ways of said cache for a line that is not also stored in another cache and replacing said line with said data; and

if said line is not found, allocating space for said data in one of said multiple ways, the one of said multiple ways dedicated to processing logic that generated said request for data.

17. The method of claim 16, wherein the predetermined number is one.

18. The method of claim 16, wherein allocating space for said data comprises using at least one of a Not Recently Used (NRU) or Least Recently Used (LRU) replacement algorithm.

19. The method of claim 16 further comprising, if a valid line is evicted from said another cache, providing the cache with a hint transaction signal that causes another line to indicate that said valid line is not stored in said another cache, said another line stored in the cache and corresponding to the valid, evicted line.

20. The method of claim 16, wherein determining whether the cache comprises said data comprises using a cache that is shared among multiple processor cores.