COHERENT DRAM PREFETCHER

• US 20090106498A1
• Filed: 10/23/2007
• Published: 04/23/2009
• Est. Priority Date: 10/23/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Hughes, William A., Kalyanasundharam, Vydhyanathan, Lepak, Kevin Michael, Smaus, Gregory William
• Application Number:
  US11/877,311
• Publication Number:
  US 20090106498A1
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

A system and method for obtaining coherence permission for speculative prefetched data. A memory controller stores an address of a prefetch memory line in a prefetch buffer. Upon allocation of an entry in the prefetch buffer a snoop of all the caches in the system occurs. Coherency permission information is stored in the prefetch buffer. The corresponding prefetch data may be stored elsewhere. During a subsequent memory access request for a memory address stored in the prefetch buffer, both the coherency information and prefetched data may be already available and the memory access latency is reduced.

Claims

1. A method comprising:

initiating a memory access for a first memory line, the memory access being initiated by a processor;

allocating an entry and storing information corresponding to a second memory line in the allocated entry, the second memory line being predicted to be required in a subsequent memory access operation;

searching cache subsystems of a computing system for copies of the second memory line, in response to said allocating;

receiving status information corresponding to said second memory line, in response to said searching; and

storing said status information in the allocated entry.

2. The method as recited in claim 1, wherein in response to a cache hit as a result of said searching, no change in ownership status of the memory line results from the cache hit.

3. The method as recited in claim 2, wherein said allocating is in response to predicting said memory line will be required on a subsequent memory access operation.

4. The method as recited in claim 1, further comprising prefetching said second memory line.

5. The method as recited in claim 4, further comprising conveying said prefetched second memory line to the processor, in response to detecting:

a request by the processor for the second memory line; and

said status information indicates said prefetched second memory line is valid.

6. The method as recited in claim 4, further comprising searching said cache subsystems for a valid copy of the second memory line, in response to detecting:

a request by the processor for the second memory line; and

said status information indicates said prefetched second memory line is not valid.

7. The method as recited in claim 1, further comprising storing a memory block address and memory line cache status corresponding to the memory block address.

8. A computer system comprising:

a processing unit comprising a plurality of processors;

a cache subsystem coupled to each processor; and

a memory controller comprising a plurality of entries coupled to the processing unit;

wherein the memory controller is configured to;

store information in an entry corresponding to a memory block, the memory block comprising a memory line predicted to be required in a subsequent memory access operation;

allocate a new entry of the plurality of entries for the memory block;

search cache subsystems of the computing system for copies of the memory block, in response to the allocating the new entry;

store status information of a copy of the memory block from the cache subsystem in the new allocated entry, in response to a hit in the cache subsystem.

9. The system as recited in claim 8, wherein the memory controller is further configured to, in response to a new allocated entry of the plurality of entries, not obtain exclusive ownership of a memory line in a cache subsystem for a cache hit.

10. The system as recited in claim 9, wherein the memory controller is further configured to, in response to a memory line predicted to be required in a subsequent memory access operation, allocate a new entry of the plurality of entries.

11. The system as recited in claim 10, wherein the memory controller is further configured to, in response to an entry of the plurality of entries selected by a memory access operation, convey data of the corresponding memory line to a requesting processor if the status information is clean.

12. The system as recited in claim 10, wherein the memory controller is further configured to, in response to an entry of the plurality of entries selected by a memory access operation, search for updated data of the corresponding memory line if the status information is modified or exclusive.

13. The system as recited in claim 11, wherein each of the entries is configured to store a memory block address and memory line cache status corresponding to the memory block address.

14. A memory controller, in one processing node within a computing system comprising a plurality of processing nodes, comprising:

a plurality of entries, wherein each of the entries is configured to store information corresponding to a memory block, the memory block comprising a memory line predicted to be required in a subsequent memory access operation; and

control logic, wherein the control logic is configured to;

search cache subsystems of the computing system for copies of the memory block; and

store status information of the copy of the memory block from the cache subsystem in the new allocated entry, in response to a hit in a cache subsystem.

15. The memory controller as recited in claim 14, wherein the control logic is further configured to, in response to a new allocated entry of the plurality of entries, not obtain exclusive ownership of a memory line in a cache subsystem for a cache hit.

16. The memory controller as recited in claim 15, wherein the control logic is further configured to, in response to a memory line predicted to be required in a subsequent memory access operation, allocate a new entry of the plurality of entries.

17. The memory controller as recited in claim 16, wherein the control logic is further configured to, in response to an entry of the plurality of entries selected by a memory access operation, convey data of the corresponding memory line to a requesting processor if the status information is clean.

18. The memory controller as recited in claim 17, wherein the control logic is further configured to, in response to an entry of the plurality of entries selected by a memory access operation, search for updated data of the corresponding memory line if the status information is modified or exclusive.

19. The memory controller as recited in claim 14, wherein each of the entries is configured to store a memory block address and memory line cache status corresponding to the memory block address.