Data cache management mechanism for packet forwarding

• US 20090106501A1
• Filed: 10/17/2007
• Published: 04/23/2009
• Est. Priority Date: 10/17/2007
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wang, Xi, Kaplan, Leo
• Application Number:
  US11/975,271
• Publication Number:
  US 20090106501A1
• Time in Patent Office: Days
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet

Abstract

There is provided a method of managing a cache memory. The method comprising resetting a flag indicative of lack of incoming data for generating a packet for forwarding; receiving the incoming data; storing the incoming data in the main memory; transferring the incoming data from the main memory into a cache buffer within the cache memory, the cache buffer having a buffer size; setting the flag indicative of the incoming data received for generating the packet for forwarding; processing the incoming data to generate the packet in the cache buffer for forwarding, the packet having a packet size; writing back the packet from the cache buffer into the main memory; first invalidating a portion of the cache buffer; transmitting the packet after the first invalidating; and second invalidating, after the transmitting, the cache buffer for the buffer size if the flag is not set by the setting.

Claims

1. A method of managing a cache memory in a communication device including a logic device, a main memory, an incoming data interface and an outgoing data interface, the method comprising:

resetting a flag indicative of lack of incoming data for generating a packet for forwarding;

receiving the incoming data by the incoming data interface;

storing the incoming data in the main memory;

transferring the incoming data from the main memory into a cache buffer within the cache memory, the cache buffer having a buffer size;

setting the flag indicative of the incoming data received for generating the packet for forwarding;

processing the incoming data to generate the packet in the cache buffer for forwarding, the packet having a packet size;

writing back the packet from the cache buffer into the main memory;

first invalidating a portion of the cache buffer;

transmitting the packet by the outgoing data interface after the first invalidating; and

second invalidating, after the transmitting, the cache buffer for the buffer size if the flag is not set by the setting.

2. The method of claim 1, wherein the first invalidating invalidates the portion of the cache buffer modified by the processing the incoming data.

3. The method of claim 1, wherein the first invalidating invalidates the cache buffer for the packet size.

4. The method of claim 1, wherein the writing back and the first invalidating occur concurrently using a single instruction.

5. The method of claim 1, wherein the logic device is a central processing unit.

6. The method of claim 1, wherein the communication device is a DSL (digital subscriber line) modem.

7. The method of claim 1, wherein the incoming data interface is in communication with a telephone line.

8. The method of claim 1, wherein the outgoing data interface is in communication with an Ethernet connection.

9. A communication device for forwarding a packet, the communication device comprising:

a logic device operable to reset a flag indicative of lack of incoming data for generating the packet for forwarding;

an incoming data interface operable to receive the incoming data;

a main memory for storing the incoming data;

a cache memory including a cache buffer, the cache buffer having a buffer size;

an outgoing data interface for forwarding the packet;

the logic device being operable to transfer the incoming data from the main memory into the cache buffer, to set the flag indicative if the incoming data are received for generating the packet for forwarding, and to process the incoming data to generate the packet in the cache buffer for forwarding, the packet having a packet size;

the logic device being operable to write back the packet from the cache buffer into the main memory, and to first invalidate a portion of the cache buffer, prior to the outgoing data interface transmitting the packet;

the logic device being operable to invalidate, after the outgoing data interface transmits the packet, the cache buffer for the buffer size if the flag is not set.

10. The communication device of claim 9, wherein the logic device is operable to first invalidate the portion of the cache buffer modified by the processing the incoming data.

11. The communication device of claim 9, wherein the logic device is operable to first invalidate the cache buffer for the packet size.

12. The communication device of claim 9, wherein the write back and the first invalidation occur concurrently using a single instruction.

13. The communication device of claim 9, wherein the logic device is a central processing unit.

14. The communication device of claim 9, wherein the communication device is a DSL (digital subscriber line) modem.

15. The communication device of claim 9, wherein the incoming data interface is in communication with a telephone line.

16. The communication device of claim 9, wherein the outgoing data interface is in communication with an Ethernet connection.