Method and Apparatus for Memory Access Optimization

• US 20090106506A1
• Filed: 10/22/2007
• Published: 04/23/2009
• Est. Priority Date: 10/22/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Lopez, Paolo Lenne, Skerlj, Maurizio
• Granted Patent: US 7,844,785 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

Access to a memory is optimized by monitoring physical memory addresses and by detecting a memory access conflict based on the monitored physical memory addresses. The data stored at a physical address for which a conflict was detected is transferred to a new physical address.

Claims

1. A memory access optimizer, comprising:

a conflict detector configured to monitor physical memory addresses and to detect a memory access conflict based on the monitored physical memory addresses; and

a storage location changer configured to transfer data stored at a physical address for which a conflict is detected to a new physical address.

2. The memory access optimizer in accordance with claim 1, wherein the memory access optimizer is configured to access a memory having a plurality of separately accessible memory portions comprising a plurality of memory elements, wherein

the conflict detector is configured to detect a conflict when two or more consecutive memory accesses are performed to different memory elements of the same memory portion.

3. The memory access optimizer in accordance with claim 2, wherein the memory access optimizer is configured to access a memory having a plurality of memory banks, each memory bank having a plurality of rows of simultaneously selectable memory elements;

and

wherein the conflict detector is configured to detect a conflict when two consecutive memory accesses are performed to different rows of the same memory bank.

4. The memory access optimizer in accordance with claim 2, wherein the storage location changer is configured to transfer the data from a memory element of a first memory portion to a memory element of a second memory portion.

5. The memory access optimizer in accordance with claim 3, wherein the storage location changer is configured to transfer the data stored in a row of a first memory bank to a row of a second memory bank.

6. The memory access optimizer in accordance with claim 1, wherein the memory access optimizer is configured to access a memory with a plurality of ranks, each rank having a plurality of memory banks, each memory bank having a plurality of rows of simultaneously selectable memory elements, wherein

the storage location changer is configured to transfer the data from a row of a memory bank of a first rank to a row of an arbitrary memory bank of a second different rank.

7. The memory access optimizer in accordance with claim 1, wherein the storage location changer is configured to transfer the data after a conflict for a same physical address was determined a predetermined number of times.

8. The memory access optimizer in accordance with claim 3, wherein the conflict detector is configured to detect a conflict when a command cycle comprising an activate, a precharge and an activate command is detected in two consecutive memory accesses for the same memory bank.

9. The memory access optimizer in accordance with claim 1, wherein the storage location changer further comprises a buffer memory configured to temporarily store the data to be transferred.

10. The memory access optimizer in accordance with claim 1, further comprising an address translator configured to replace the physical address by the new physical address for physical addresses from which data was transferred.

11. The memory access optimizer in accordance with claim 10, further comprising:

a memory interface configured to physically access the memory using the physical address provided by the address translator.

12. The memory access optimizer in accordance with claim 10, wherein the address translator further comprises an input interface configured to receive memory addresses to be accessed.

13. The memory access optimizer in accordance with claim 1, wherein the conflict detector is configured to detect memory access conflicts associated to read operations.

14. The memory access optimizer in accordance with claim 1, wherein the memory access optimizer is adapted to optimize the memory access to a memory having a plurality of banks, each bank having a plurality of rows of simultaneously selectable memory elements, wherein:

the conflict detector is configured to detect a memory access conflict when consecutive memory accesses are performed to different rows within the same bank; and

the storage location changer is configured to transfer data stored in a row for which a conflict has been detected to a new row of a different bank.

15. A memory access optimizer, comprising:

a conflict detector configured to monitor physical memory addresses and to detect a memory access conflict based on the monitored physical memory addresses;

a storage location changer configured to transfer data stored at a physical address for which a conflict is detected to a new physical address;

an address translator configured to receive memory addresses and to translate the received addresses to physical memory addresses, the address translator being further configured to replace the physical addresses by the new physical addresses for physical addresses from which data has been transferred by the storage location changer; and

a memory interface configured to physically access the memory using the physical address provided by the address translator.

16. A memory system, comprising:

a memory access optimizer, comprising;

a conflict detector configured to monitor physical memory addresses and for detecting a memory access conflict based on the monitored physical memory addresses; and

a storage location changer configured to transfer data stored at a physical address for which a conflict is detected to a new physical address; and

a memory accessible using physical memory addresses, the memory comprising the physical address and the new physical address.

17. A method for memory access optimization, the method comprising:

monitoring physical memory addresses for detecting a memory access conflict based on the monitored memory addresses; and

transferring data stored at a physical address for which a conflict is detected to a new physical address.

18. The method in accordance with claim 17, wherein the method is adapted to optimize the access to a memory having a plurality of separately accessible memory portions comprising a plurality of memory elements, in which a conflict is detected when two consecutive memory accesses are performed to different memory elements of the same memory portion.

19. The method in accordance with claim 18, wherein the data is transferred from a memory element of a first memory portion to a memory element of a second memory portion.

20. The method in accordance with claim 17, wherein the data is transferred after the same memory conflict has been detected for a predetermined number of times.

21. The method in accordance with claim 17, wherein the method is adapted to optimize the access to a memory having a plurality of banks, each bank having a plurality of rows of simultaneously selectable memory elements, wherein:

a memory access conflict is detected, when consecutive memory accesses are performed to different rows within the same memory bank; and

data stored in a row for which a conflict was detected is transferred to a row in a different bank.

22. An apparatus for optimizing memory access, the apparatus comprising:

means for monitoring physical memory addresses and for detecting a memory access conflict based on the monitored physical memory addresses; and

means for transferring data stored at a physical address for which a conflict was detected to a new physical address.