Memory System and Method for Using a Memory System with Virtual Address Translation Capabilities

• US 20090106507A1
• Filed: 10/22/2007
• Published: 04/23/2009
• Est. Priority Date: 10/22/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Skerlj, Maurizio, Lopez, Paolo Ienne
• Granted Patent: US 8,185,716 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A memory system comprises a first memory having associated therewith a first local memory access controller configured to access the first local memory using physical memory addresses and a second memory having associated therewith a second local memory access controller configured to access the second local memory using physical memory addresses. A global controller coupled to the first and second local controllers is configured to communicate virtual memory addresses to the first and second local memory controllers.

Claims

1. A memory system, comprising:

a first memory having associated therewith a first local memory access controller configured to access the first local memory using physical memory addresses;

a second memory having associated therewith a second local memory access controller configured to access the second local memory using physical memory addresses; and

a global controller coupled to the first and second local controllers, the global controller configured to communicate virtual memory addresses to the first and second local memory controllers.

2. The memory system in accordance with claim 1, wherein the global controller is further operative to communicate search queries in association with a virtual memory address.

3. The memory system in accordance with claim 1, wherein the first local memory access controller comprises a first query processor and the second local memory access controller comprises a second query processor, the query processors configured to answer search queries using data stored at a physical memory address associated to a communicated virtual address.

4. A memory arrangement with memory accessible using physical memory addresses, the memory arrangement comprising:

a local memory access controller configured to receive physical memory addresses and virtual memory addresses from a global controller, the local memory access controller further configured to translate the received virtual memory addresses to associated physical memory addresses; and

a memory interface for accessing the memory using the physical memory addresses.

5. The memory arrangement in accordance with claim 4, wherein the local memory access controller is further configured to receive memory translation information indicating an association between a physical memory address and a virtual memory address.

6. The memory arrangement in accordance with claim 4, wherein the memory access controller is further configured to receive a translation requirement signal, indicating whether a received address shall be translated.

7. The memory arrangement in accordance with claim 6, wherein the translation requirement signal comprises a signal bit or a bit sequence transmitted on one or more bit lines.

8. The memory arrangement in accordance with claim 4, wherein the local memory access controller further comprises a translation look-aside buffer configured to contain virtual memory addresses and their associated physical memory addresses.

9. The memory arrangement in accordance with claim 4, wherein the local memory access controller comprises a memory configured to store a page table.

10. The memory arrangement in accordance with claim 4, wherein the local memory access controller is further configured to communicate to the global controller, when a translation of the virtual address was unsuccessful.

11. The memory arrangement in accordance with claim 4, wherein the local memory access controller is further configured to transfer data stored at a received physical memory address to the global controller.

12. The memory arrangement in accordance with claim 4, wherein the local memory access controller is further configured to issue an allocation request to the global controller, indicating that the global controller shall allocate memory associated to the local memory access controller using physical addresses.

13. The memory arrangement in accordance with claim 4, wherein the local memory access controller is further operative to receive search queries in association with a virtual memory address.

14. The memory arrangement in accordance with claim 13, wherein the local memory access controller further comprises a query processor configured to answer search queries using data stored at the physical memory address associated to the transmitted virtual address.

15. The memory arrangement in accordance with claim 14, wherein the query processor is further configured to store result data of the answer of the search query in the memory associated to the local memory access controller.

16. The memory arrangement in accordance with claim 15, wherein the local memory access controller is further operative to communicate a physical address of a storage location of the result data to the global controller.

17. A memory arrangement, comprising:

a first memory having associated therewith a first local memory access controller configured to translate a received virtual memory address to a corresponding physical memory address when the corresponding physical memory address is associated to the first memory; and

a second memory having associated therewith a second local memory access controller configured to translate a received virtual memory address to a corresponding physical memory address when the corresponding physical memory address is associated to the second memory.

18. A method for accessing memory, the method comprising:

receiving physical memory addresses and virtual memory addresses from a global controller;

translating the received virtual memory addresses to associated physical memory addresses; and

accessing the memory using the physical memory addresses.

19. The method in accordance with claim 18, further comprising receiving memory translation information indicating an association between a physical memory address and a virtual memory address, the translating being based at least in part of the received memory translation information.

20. The method in accordance with claim 18, further comprising receiving a translation requirement signal, indicating that a received address must be translated.

21. The method in accordance with claim 18, further comprising communicating to the global controller when a translation of a virtual address was unsuccessful.

22. The method in accordance with claim 18, further comprising receiving search queries in association with a virtual memory address.

23. The method in accordance with claim 18, further comprising storing result data of an answer to the search query within the memory.

24. A method for accessing data in a memory system, the method comprising:

accessing a first local memory with a first local memory access controller using physical memory addresses;

accessing a second local memory with a second local memory access controller using physical memory addresses; and

communicating virtual memory addresses to the first and second local memory access controllers.