LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE

• US 20090106626A1
• Filed: 10/23/2007
• Published: 04/23/2009
• Est. Priority Date: 10/23/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Gershon, Eugen, Hou, Ping
• Granted Patent: US 8,301,963 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1197 Irregular repeat-accumulate [IRA] codes

Abstract

An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on certain probability calculations as to the values of the read data. The decoder component can analyze a decoding result and reference a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result can be representation of the original data and can be provided as an output.

Claims

1. A system that facilitates error correction of data, comprising:

a memory that stores the data and parity data associated with the data; and

a decoder component that decodes the data based in part on the parity data to facilitate error correction of the data.

2. The system of claim 1, the parity data is based in part on a low-density parity-check code.

3. The system of claim 1, the decoder component performs one or more iterations to decode the data read from the memory and ceases to decode the data when at least one of a predetermined threshold level of accuracy associated with error correction of data is obtained or a predetermined maximum number of iterations is performed.

4. The system of claim 1, the decoder component receives information associated with at least one of a first matrix or a second matrix, or a combination thereof, to facilitate error correction of the data, the second matrix is based in part on a low-density parity-check code.

5. The system of claim 1, further comprising a translation component that translates at least one of multiplication operations or division operations, or a combination thereof, associated with error correction of the data into the log domain such that multiplication operations are translated to addition operations and division operations are translated to subtraction operations in the log domain.

6. The system of claim 1, further comprising an accumulative repeat encoder component that generates parity data related to the data based in part on information associated with a first matrix and generates parity data related to the data based in part on information associated with a second matrix based in part on a low-density parity-check code to facilitate error correction of the data.

7. The system of claim 6, the accumulative repeat encoder component further comprises an integrator component and an adder component, the accumulative repeat encoder component feeds an output comprised of respective matrix multiplication results of the first matrix and the data into the adder component to sum the respective matrix multiplication results, wherein the sum of the respective matrix multiplication results is provided to the integrator component that processes the sum based in part on a transfer function associated with the second matrix to facilitate generation of the parity data based in part on the second matrix.

8. The system of claim 1, further comprising a memory module, the memory module includes at least one of the memory, a cryptographic component, an accumulative repeat encoder component, a decoder component, an analog-to-digital converter, a digital-to-analog converter, or a storage component, or a combination thereof, and the memory module is formed on a single integrated-circuit chip.

9. The system of claim 1, the memory is a non-volatile memory that is at least one of flash memory, multi-bit flash memory, read only memory (ROM), programmable ROM (PROM), erasable programmable read only memory (EPROM), or electronically erasable programmable read only memory (EEPROM), or a combination thereof.

10. The system of claim 1, further comprising a host processor that generates at least one of a write command, a read command, or an erase command, or a combination thereof.

11. An electronic device comprising the system of claim 1, the electronic device is one of a computer, a cellular phone, a digital phone, a video device, a smart card, a personal digital assistant, a television, an electronic game, a digital camera, an electronic organizer, an audio player, an audio recorder, an electronic device associated with digital rights management, Personal Computer Memory Card International Association (PCMCIA) cards, trusted platform modules (TPMs), Hardware Security Modules (HSMs), set-top boxes, secure portable tokens, Universal Serial Bus (USB) tokens, key tokens, secure memory devices with computational capabilities, electronic devices with tamper-resistant chips, a navigation system, an electronic device associated with an industrial control system, or an embedded computer in a machine, wherein the machine comprises one of an airplane, a copier, a motor vehicle, or a microwave oven.

12. A method that facilitates error correcting data, comprising:

decoding the data based in part on parity data associated with the data, the parity data is based in part on a low-density parity-check code to facilitate error correcting the data; and

providing the decoded data.

13. The method of claim 12, further comprising:

encoding the data based in part on a first matrix, to yield a sequence of matrix multiplication results associated with a matrix multiplication of the data and the first matrix, the data comprising a sequence of pieces of data;

adding respective matrix multiplication results of the sequence of matrix multiplication results;

providing the added respective matrix multiplication results;

integrating the added respective matrix multiplication results based in part on a transfer function;

generating parity data associated with the data based in part on a second matrix, the second matrix is based in part on the low-density parity-check code and is associated with the transfer function; and

providing the data and the parity data associated with the data as an output.

14. The method of claim 13, further comprising:

converting the encoded data into at least one analog signal that corresponds to the encoded data; and

storing the at least one analog signal in at least one memory location in a memory.

15. The method of claim 12, further comprising:

retrieving at least one analog signal from a memory, the at least one analog signal corresponds to the encoded data; and

converting the at least one analog signal into at least one sequence associated with the encoded data.

16. The method of claim 15, further comprising:

receiving one or more symbols associated with the data;

calculating at least probability associated with determining a respective value of the one or more symbols to yield at least one decoding result associated with the data;

retrieving information associated with at least one of a first matrix and a second matrix, or a combination thereof, associated with the parity data, the second matrix is structured based in part on a low-density parity-check code;

comparing the decoding result with the information associated with at least one of a first matrix and a second matrix, or a combination thereof;

determining if the decoding result meets a predetermined accuracy criteria with regard to the data; and

at least one of;

providing the decoding result if the decoding result meets a predetermined accuracy criteria with regard to the data, or

performing at least one other act associated with the data if the decoding result does not meet the predetermined accuracy criteria with regard to the data.

17. The method of claim 16, the performing at least one other act associated with the data if the decoding result does not meet the predetermined accuracy criteria with regard to the data, further comprising:

determining if a predetermined maximum number of decoding iterations has been performed; and

at least one of;

performing at least one additional decoding iteration if the maximum number of decoding iterations has not been performed, or

providing as an output at least one of a decoding result associated with a current decoding iteration, or an error message, or a combination thereof, if the maximum number of decoding iterations has been performed.

18. The method of claim 12, further comprising:

translating at least one mathematical operation associated with decoding the data into at least one disparate mathematical operation in a log domain, the at least one mathematical operation is at least one of an multiplication operation or a division operation, or a combination thereof, and the at least one disparate mathematical operation is at least one of an addition operation or a subtraction operation, or a combination thereof.

19. A system for decoding data, comprising:

means for decoding the data based in part on parity data associated with a low-density parity-check code to facilitate error correction of the data, the parity data is associated with the data; and

means for providing the decoded data.

20. The system of claim 19, further comprising:

means for encoding the data based in part on at least one of a first matrix or a second matrix, or a combination thereof, the second matrix is associated with a low-density parity-check code;

means for converting the encoded data into at least one analog signal, the at least one analog signal corresponds to the encoded data;

means for storing the at least one analog signal;

means for retrieving the at least one analog signal; and

means for converting the at least one analog signal into at least one sequence associated with the data.