Multiple Source-Single Drain Field Effect Semiconductor Device and Circuit
First Claim
1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising a field effect transistor comprising:
- an output diffusion region;
a plurality of input diffusion regions; and
a gate structure comprising;
a main body between said input diffusion regions and said output diffusion region; and
a plurality of extensions that project outward from said main body between adjacent input diffusion regions.
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Accused Products
Abstract
Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
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Citations
20 Claims
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1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising a field effect transistor comprising:
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an output diffusion region; a plurality of input diffusion regions; and a gate structure comprising; a main body between said input diffusion regions and said output diffusion region; and a plurality of extensions that project outward from said main body between adjacent input diffusion regions. - View Dependent Claims (2, 3, 4, 5)
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6. A design structure embodied in a machine readable medium used in a design process, the design structure comprising a phase adjusting circuit comprising:
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an input node for receiving a first signal; a variable-delay field effect transistor comprising; an output diffusion region; a plurality of input diffusion regions; and a gate structure connected to said input node and comprising; a main body between said input diffusion regions and said output diffusion region; and a plurality of extensions that project outward from said main body between adjacent input diffusion regions, wherein said input diffusion regions are adapted to be selectively biased in order to selectively vary delay of said variable-delay field effect transistor, wherein said output diffusion region is adapted to receive, from a biased input diffusion region, a second signal, and wherein a phase difference between said first signal and said second signal is based on said delay; an output node connected to said output diffusion region; and a current source connected to said output node and adapted to bias said output node when said variable-delay field effect transistor is off. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A design structure embodied in a machine readable medium used in a design process, the design structure comprising a phase adjusting mixer circuit comprising:
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an input node for receiving a first signal; a variable-delay field effect transistor comprising; an output diffusion region; and a plurality of input diffusion regions; and a gate structure connected to said input node and comprising; a main body between said input diffusion regions and said output diffusion region; and a plurality of extensions that project outward from said main body between adjacent input diffusion regions, wherein said input diffusion regions are adapted to be selectively biased in order to selectively vary delay of said variable-delay field effect transistor, wherein said output diffusion region is adapted to receive, from a biased input diffusion region, a second signal, and wherein a phase difference between said first signal and said second signal is based on said delay; an output node electrically connected to said output diffusion region; and a current source connected to said output node and adapted to transmit a third signal to said output node, wherein said current source is non-constant, and wherein said output node is adapted to combine said second signal and said third signal. - View Dependent Claims (18, 19, 20)
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Specification