Multiple Source-Single Drain Field Effect Semiconductor Device and Circuit

• US 20090106707A1
• Filed: 10/17/2007
• Published: 04/23/2009
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Iadanza, Joseph A., Bonaccio, Anthony R., Abadeer, Wagdi W.
• Granted Patent: US 7,814,449 B2
• Time in Patent Office: Days
• US Class Current: 716/100
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.

Claims

1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising a field effect transistor comprising:

an output diffusion region;

a plurality of input diffusion regions; and

a gate structure comprising;

a main body between said input diffusion regions and said output diffusion region; and

a plurality of extensions that project outward from said main body between adjacent input diffusion regions.

2. The design structure according to claim 1, all the limitations of which are incorporated herein by reference, wherein said input diffusion regions are adapted to be selectively biased in order selectively vary delay of said field effect transistor.

3. The design structure according to claim 1, all the limitations of which are incorporated herein by reference, wherein said design structure comprises a netlist which describes a circuit.

4. The design structure according to claim 1, all the limitations of which are incorporated herein by reference, wherein said design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.

5. The design structure according to claim 1, all the limitations of which are incorporated herein by reference, wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.

6. A design structure embodied in a machine readable medium used in a design process, the design structure comprising a phase adjusting circuit comprising:

an input node for receiving a first signal;

a variable-delay field effect transistor comprising;

an output diffusion region;

a plurality of input diffusion regions; and

a gate structure connected to said input node and comprising;

a main body between said input diffusion regions and said output diffusion region; and

a plurality of extensions that project outward from said main body between adjacent input diffusion regions,

wherein said input diffusion regions are adapted to be selectively biased in order to selectively vary delay of said variable-delay field effect transistor,

wherein said output diffusion region is adapted to receive, from a biased input diffusion region, a second signal, and

wherein a phase difference between said first signal and said second signal is based on said delay;

an output node connected to said output diffusion region; and

a current source connected to said output node and adapted to bias said output node when said variable-delay field effect transistor is off.

7. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, wherein said gate structure is further adapted to propagate said first signal through segments of said main body sequentially.

8. The design structure according to claim 7, all the limitations of which are incorporated herein by reference, wherein, if a single input diffusion region is selectively biased, said first signal is propagated through said segments of said main body such that, when an active edge of said first signal passes through a gate segment corresponding to said single input diffusion region, a channel is enabled and said second signal is transmitted to said output diffusion region, and such that, when an inactive edge of said first signal passes through said gate segment, transmission of said second signal is broken.

9. The design structure according to claim 7, all the limitations of which are incorporated herein by reference, wherein, if a plurality of input diffusion regions are selectively biased, said first signal is propagated through said segments of said main body such that, when an active edge of said first signal passes through a first gate segment corresponding to a first biased input diffusion region, a channel is enabled and said second signal is transmitted to said output diffusion region, and such that, when an inactive edge of said first signal passes through a last gate segment corresponding to a last biased input diffusion region, transmission of said second signal is broken.

10. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, further comprising switches connected between said input diffusion regions and a voltage rail so as to allow selective biasing of said input diffusion regions.

11. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, further comprising silicide regions on only selected portions of a top surface of said gate structure such that resistance across said gate structure and, thereby, said delay is tailored.

12. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, further comprising at least one capacitor electrically connected to at least one of said extensions.

13. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, wherein said main body is one of:

non-linear and positioned so as to at least partially wrap around said output diffusion region; and

linear and positioned adjacent only one side of said output diffusion region.

14. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, wherein said design structure comprises a netlist which describes a circuit.

15. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, wherein said design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.

16. The design structure according to claim 6, all the limitations of which are incorporated herein by reference, wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.

17. A design structure embodied in a machine readable medium used in a design process, the design structure comprising a phase adjusting mixer circuit comprising:

an input node for receiving a first signal;

a variable-delay field effect transistor comprising;

an output diffusion region; and

a plurality of input diffusion regions; and

a gate structure connected to said input node and comprising;

a main body between said input diffusion regions and said output diffusion region; and

a plurality of extensions that project outward from said main body between adjacent input diffusion regions,

wherein said input diffusion regions are adapted to be selectively biased in order to selectively vary delay of said variable-delay field effect transistor,

wherein said output diffusion region is adapted to receive, from a biased input diffusion region, a second signal, and

wherein a phase difference between said first signal and said second signal is based on said delay;

an output node electrically connected to said output diffusion region; and

a current source connected to said output node and adapted to transmit a third signal to said output node,

wherein said current source is non-constant, and

wherein said output node is adapted to combine said second signal and said third signal.

18. The design structure according to claim 17, all the limitations of which are incorporated herein by reference, wherein said design structure comprises a netlist which describes a circuit.

19. The design structure according to claim 17, all the limitations of which are incorporated herein by reference, wherein said design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.

20. The design structure according to claim 17, all the limitations of which are incorporated herein by reference, wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.