THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20090108256A1
• Filed: 08/06/2008
• Published: 04/30/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kong, Hyang-Shik, Kwak, Sang-Ki, Kim, Sun-Il
• Granted Patent: US 8,183,097 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Claims

1. A thin-film transistor (TFT) substrate comprising:

a semiconductor pattern formed on a substrate;

a conductive pattern formed as a layer identical to the semiconductor pattern on the substrate;

a first wiring pattern formed on the semiconductor pattern, the first wiring pattern comprising a source electrode and a drain electrode spaced apart from the source electrode;

an insulation pattern formed on the substrate having the first wiring pattern to cover the first wiring pattern; and

a second wiring pattern formed on the insulation pattern, the second wiring pattern comprising a gate electrode formed on the source and drain electrodes.

2. The TFT substrate of claim 1, wherein the semiconductor pattern includes a metal oxide semiconductor.

3. The TFT substrate of claim 2, wherein the metal oxide semiconductor includes zinc oxide (ZnO).

4. The TFT substrate of claim 3, wherein the metal oxide semiconductor includes at least one of indium (In) and gallium (Ga).

5. The TFT substrate of claim 2, wherein the conductive pattern includes a conductive oxide material formed through a plasma process of the metal oxide semiconductor.

6. The TFT substrate of claim 1, wherein the first wiring pattern further comprises a data line electrically connected to the source electrode.

7. The TFT substrate of claim 6, wherein the conductive pattern comprises:

a pixel electrode electrically connected to the drain electrode; and

a data pad electrically connected to the data line.

8. The TFT substrate of claim 1, wherein the second wiring pattern further comprises:

a gate line electrically connected to the gate electrode; and

a gate pad electrically connected to the gate line.

9. The TFT substrate of claim 1, wherein the first wiring pattern further comprises a first maintaining electrode for forming a maintaining capacitor, and

the second wiring pattern further comprises a second maintaining electrode overlapping the first maintaining electrode to form a maintaining capacitor.

10. The TFT substrate of claim 1, further comprising:

a color filter layer formed on a substrate having the second wiring pattern;

and

a black matrix formed on the substrate having the second wiring pattern.

11. A thin-film transistor (TFT) substrate comprising:

a semiconductor pattern formed on a substrate, the semiconductor pattern including a metal oxide semiconductor;

a first wiring pattern formed on the semiconductor pattern, the first wiring pattern comprising a source electrode and a drain electrode spaced apart from the source electrode;

an insulation pattern formed on the substrate having the first wiring pattern, the insulation pattern covering the first wiring pattern;

a second wiring pattern formed on the insulation pattern, the second wiring pattern comprising a gate electrode formed on the source and drain electrodes; and

a conductive pattern formed on the substrate, the conductive pattern including a pixel electrode electrically connected to the drain electrode.

12. The TFT substrate of claim 11, further comprising:

a color filter layer formed on the substrate having the second wiring pattern; and

a light-blocking layer formed on the substrate having the second wiring pattern,

wherein the conductive pattern is formed on the color filter layer and the light-blocking layer.

13. A method of manufacturing a thin-film transistor (TFT) substrate, the method comprising:

forming a semiconductor pattern layer on a substrate and a first wiring pattern on the semiconductor pattern layer using a first mask, the first wiring pattern including a source electrode and a drain electrode spaced apart from the source electrode;

forming an insulation layer pattern covering the first wiring pattern and a second wiring pattern on the insulation layer pattern using a second mask, the second wiring pattern including a gate electrode formed on the source and drain electrodes; and

forming a conductive pattern and a semiconductor pattern through a plasma process on a portion of the semiconductor pattern layer.

14. The method of claim 13, wherein forming the semiconductor pattern layer and the first wiring pattern comprises:

forming a metal oxide semiconductor and then a first conductive layer;

forming a first photoresist pattern on the first conductive layer using the first mask;

etching the first conductive layer and the metal oxide semiconductor to form a first conductive pattern layer from the first conductive layer and a second conductive pattern layer from the metal oxide semiconductor layer;

performing an etch back process to the first photoresist pattern to form a second photoresist pattern; and

etching the first conductive pattern to form the first wiring pattern.

15. The method of claim 14, wherein forming the insulation layer pattern and the second wiring pattern comprises:

forming an insulation layer and then a second conductive layer on a substrate having the first wiring pattern;

forming a third photoresist pattern on the second conductive layer using the second mask;

etching the second conductive layer to form a second conductive pattern layer;

etching the insulation layer to form the insulation layer pattern;

performing an etch back process to the third photoresist pattern to form a fourth photoresist pattern; and

etching the second conductive pattern layer to form a second wiring pattern.

16. The method of claim 15, in etching the insulation layer to form the insulation layer pattern, wherein the insulation layer is etched to expose a portion of an edge of the first wiring pattern.

17. The method of claim 16, wherein the plasma process of the semiconductor pattern layer uses the first and second wiring patterns as a mask.

18. The method of claim 13, further comprising forming a color filter layer and a black matrix after forming the conductive pattern and the semiconductor pattern.

19. A method of manufacturing a thin-film transistor (TFT) substrate, the method comprising:

forming a semiconductor pattern on a substrate and a first wiring pattern on the semiconductor pattern using a first mask, the semiconductor pattern including a metal oxide semiconductor, and the first wiring pattern including a source electrode and a drain electrode spaced apart from the source electrode;

forming an insulation layer pattern covering the first wiring pattern and a second wiring pattern on the insulation layer pattern using a second mask, the second wiring pattern including a gate electrode formed on the source and drain electrodes; and

forming a conductive pattern on the insulation layer pattern using a third mask, the conductive pattern including a pixel electrode electrically connected to the drain electrode.

20. The method of claim 19, further comprising forming a color filter layer and a light-blocking layer after forming the insulation layer pattern and the second wiring pattern.