PIXEL STRUCTURE AND FABRICATION METHOD THEREOF

• US 20090108280A1
• Filed: 12/05/2007
• Published: 04/30/2009
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Lin, Han-Tu, Jan, Shiun-Chang
• Granted Patent: US 7,935,583 B2
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A fabrication method of a pixel structure includes utilizing only a single photomask in two different lithographic processes for defining patterns of the source/drain and passivation layer respectively. Therefore, the total amount of photomasks of the fabrication process can be decreased.

Claims

1. A fabrication method of a pixel structure, comprising:

providing a substrate;

forming a gate and a pixel electrode on the substrate;

forming a dielectric layer and a semiconductor layer on the substrate;

patterning the dielectric layer and the semiconductor layer to form a patterned dielectric layer and a patterned semiconductor layer on the gate;

forming a conductive layer on the substrate;

providing a photomask and performing a first lithographic process to pattern the conductive layer by utilizing the photomask to form a source and a drain on the patterned semiconductor layer, the drain being electrically connected to the pixel electrode;

forming a passivation layer on the substrate; and

performing a second lithographic process by utilizing the photomask to form a patterned passivation layer covering the source, the drain and the semiconductor layer and exposing a part of the pixel electrode.

2. The fabrication method of claim 1, wherein the patterned passivation layer covers sidewall surfaces of the source and the drain.

3. The fabrication method of claim 1, wherein the patterned passivation layer is at least 0.5 μ

m wider than the size of the source or the drain.

4. The fabrication method of claim 1, wherein the step of forming the patterned passivation layer by the second lithographic process comprises:

forming a photoresist layer on the passivation layer;

patterning the photoresist layer by utilizing the photomask to form a plurality of the patterns of the patterned photoresist layer, wherein the patterns of the patterned photoresist layer are wider than the source and the drain;

performing an etching process by utilizing the patterned photoresist layer as a mask to remove a part of the passivation layer not covered with the photoresist layer; and

removing the remnant photoresist layer.

5. The fabrication method of claim 1, wherein the passivation layer comprises a photosensitive material, and the step of forming the patterned passivation layer by the second lithographic process comprises:

defining patterns of the photomask on the passivation layer by utilizing the photomask; and

performing a developing process to remove a part of the passivation layer not containing the patterns of the photomask.

6. The fabrication method of claim 5, further comprising reflowing a part of the passivation layer containing the patterns of the photomask.

7. The fabrication method of claim 1, wherein the step of forming the gate and the pixel electrode on the substrate comprises:

forming a transparent conductive layer on the substrate;

forming a metal layer on the transparent conductive layer; and

patterning the transparent conductive layer and the metal layer to form the gate and the pixel electrode, wherein the gate comprises the transparent conductive layer and the metal layer, and the pixel electrode comprises the transparent conductive layer.

8. The fabrication method of claim 1, further comprising forming a channel passivation layer on the patterned semiconductor layer.

9. A fabrication method of a pixel structure, comprising:

providing a substrate;

forming a transparent conductive layer and a metal layer on the substrate in sequence;

patterning the transparent conductive layer and the metal layer to form a gate and a pixel electrode stack layer, wherein the gate and the pixel electrode stack layer both comprise the transparent conductive layer and the metal layer;

forming a dielectric layer and a semiconductor layer on the substrate;

patterning the dielectric layer and the semiconductor layer to form a patterned dielectric layer and a patterned semiconductor layer on the gate;

forming a conductive layer covering the substrate;

providing a photomask and performing a first lithographic process to pattern the conductive layer and the metal layer by utilizing the photomask so as to form a source and a drain and to expose a part of the transparent conductive layer of the pixel electrode stack layer as a pixel electrode;

forming a passivation layer on the substrate; and

performing a second lithographic process by utilizing the photomask to form a patterned passivation layer covering the source, the drain and the semiconductor layer and expose a part of the pixel electrode.

10. The fabrication method of claim 9, wherein the patterned passivation layer covers sidewall surfaces of the source and the drain.

11. The fabrication method of claim 9, wherein the patterned passivation layer is at least 0.5 μ

m wider than the source or the drain.

12. The fabrication method of claim 9, wherein the step of forming the patterned passivation layer by the second lithographic process comprises:

forming a photoresist layer on the passivation layer;

patterning the photoresist layer by utilizing the photomask to form a plurality of the patterns of the patterned photoresist layer, wherein the patterns of the patterned photoresist layer is wider than the source and the drain;

performing an etching process by utilizing the patterned photoresist layer as a mask to remove a part of the passivation layer not covered with the photoresist layer; and

removing the remnant photoresist layer.

13. The fabrication method of claim 9, wherein the passivation layer comprises an organic photosensitive material, and the step of forming the patterned passivation layer by the second lithographic process comprises:

defining patterns of the photomask on the passivation layer by utilizing the photomask; and

performing a developing process to remove a part of the passivation layer not containing the patterns of the photomask; and

reflowing a part of the passivation layer containing the patterns of the photomask.

14. The fabrication method of claim 9, further comprising forming a channel passivation layer on the semiconductor layer.

15. The fabrication method of claim 9, further comprising forming a capacitor on the substrate, wherein the step of forming the capacitor comprising:

forming a capacitor bottom electrode on the substrate when patterning the transparent conductive layer and the metal layer;

forming the patterned dielectric layer and the patterned semiconductor layer on the capacitor bottom electrode simultaneously when patterning the dielectric layer and the semiconductor layer; and

forming a capacitor top electrode composed of the conductive layer on the patterned semiconductor layer when patterning the conductive layer and the metal layer.

16. The fabrication method of claim 15, wherein the capacitor bottom electrode comprises the transparent conductive layer and the metal layer.

17. The fabrication method of claim 9, further comprising forming a capacitor on the substrate, wherein the step of forming the capacitor comprises:

forming a capacitor bottom electrode on the substrate when patterning the transparent conductive layer and the metal layer;

forming the patterned dielectric layer on the capacitor bottom electrode simultaneously when patterning the dielectric layer and the semiconductor layer; and

forming a capacitor top electrode composed of the conductive layer on the patterned dielectric layer simultaneously when patterning the conductive layer and the metal layer.

18. The fabrication method of claim 17, wherein the step of patterning the dielectric layer and the semiconductor layer comprises a half-tone photomask process, a gray-tone photomask process or utilizing two photomasks with different exposure dose tunings.

19. The fabrication method of claim 9, further comprising forming a pad on the substrate, wherein the step of forming the pad comprises:

forming a pad stack layer composed of the transparent conductive layer and the metal layer on the substrate when patterning the transparent conductive layer and the metal layer; and

exposing a part of the transparent conductive layer of the pad stack layer as the pad when patterning the conductive layer and the metal layer.

20. A pixel structure, comprising:

a substrate;

a gate and a pixel electrode, disposed on the substrate;

a patterned dielectric layer and a patterned semiconductor layer, disposed on the gate;

a source and a drain disposed on two sides of the patterned semiconductor layer respectively; and

a passivation layer disposed on the source, the drain and the semiconductor layer, the passivation layer completely covering sidewall surfaces of the source and the drain and exposing a part of the pixel electrode.

22. The pixel structure of claim 20, wherein the drain covers a part of surface of the pixel electrode.

23. The pixel structure of claim 20, wherein the gate comprises a transparent conductive layer and a metal layer disposed on the transparent conductive layer.

24. The pixel structure of claim 20, further comprising a channel passivation layer disposed on the semiconductor layer.

21. The pixel structure of claim 21, wherein the passivation layer is at least 0.5 μ

m wider than the source or the drain.