TRANSISTOR AND METHOD OF FABRICATING THE SAME

• US 20090108308A1
• Filed: 10/27/2008
• Published: 04/30/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Jusung Engineering Company Limited
• Original Assignee: Jusung Engineering Company Limited
• Inventors: YANG, Cheol Hoon, JEON, Yong Han
• Granted Patent: US 7,943,969 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.

Claims

1. A transistor, comprising:

a gate electrode formed on a substrate;

a first epitaxial layer that contains Ge and is formed in a recess region of the substrate at both sides of the gate electrode; and

a second epitaxial layer that has lower Ge concentration than that of the first epitaxial layer and is formed at least one of under and on the first epitaxial layer.

2. The transistor of claim 1, wherein the first epitaxial layer comprises a SiGe layer and the concentration of Ge of the SiGe layer is in a range of approximately 25% to approximately 50%.

3. The transistor of claim 1, wherein the second epitaxial layer comprises a SiGe layer and the concentration of Ge of the SiGe layer is in a range of approximately 5% to approximately 15%.

4. The transistor of claim 3, wherein the concentration of Ge contained in the second epitaxial layer formed on the first epitaxial layer is decreased as going from a lower portion to an upper portion.

5. The transistor of claim 3, wherein the concentration of Ge contained in the second epitaxial layer formed under the first epitaxial layer is increased as going from a lower portion to an upper portion.

6. The transistor of claim 1, further comprising a silicide layer formed on the gate electrode, the first epitaxial layer or the second epitaxial layer that is formed on the first epitaxial layer.

7. The transistor of claim 1, further comprising a silicon layer formed on the second epitaxial layer that is formed on the first epitaxial layer.

8. The transistor of claim 7, further comprising a silicide layer formed on the silicon layer and the gate electrode.

9. A method of fabricating a transistor, the method comprising:

forming a gate electrode over a given portion of a substrate;

forming a recess region by etching predetermined portions of the substrate at both sides of the gate electrode;

forming a first epitaxial layer containing Ge in the recess region; and

forming a second epitaxial layer whose Ge concentration is lower than that of the first epitaxial layer, wherein the second epitaxial layer is formed at least one of under and on the first epitaxial layer.

10. The method of claim 9, wherein the first and the second epitaxial layers comprises a SiGe layer.

11. The method of claim 9, wherein the second epitaxial layer formed on the first epitaxial layer is formed so that Ge concentration is decreased as going from a lower portion to an upper portion.

12. The method of claim 9, wherein the second epitaxial layer formed under the first epitaxial layer is formed so that Ge concentration is increased as going from a lower portion to an upper portion.

13. The method of claim 9, wherein forming the first epitaxial layer and forming the second epitaxial layer are continuously performed.

14. The method of claim 9, further comprising forming a silicide layer on the gate electrode, the first epitaxial layer or the second epitaxial layer that is formed on the first epitaxial layer.

15. The method of claim 9, further comprising forming a silicon layer on the first epitaxial layer or the second epitaxial layer.

16. The method of claim 15, further comprising forming a silicide layer on the silicon layer and the gate electrode.