Method For Fabricating Super-Steep Retrograde Well Mosfet On SOI or Bulk Silicon Substrate, And Device Fabricated In Accordance With The Method

• US 20090108350A1
• Filed: 10/26/2007
• Published: 04/30/2009
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cai, Jin, Ning, Tak H., Majumdar, Amlan, Ren, Zhibin
• Granted Patent: US 8,329,564 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

Claims

1. A method to fabricate a semiconductor device, comprising:

providing a substrate comprised of crystalline silicon;

implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well implant doping profile;

annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon; and

prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate.

2. The method of claim 1, where the silicon cap layer is comprised of undoped silicon to provide an undoped channel region for the semiconductor device.

3. The method of claim 1, where depositing the silicon cap layer is performed with a silicon epitaxy process at a temperature at or below about 700°

C. to maintain the desired super-steep retrograde well implant doping profile.

4. The method of claim 1, further comprising performing the shallow trench isolation process by defining an active device area on top of the silicon cap layer with padfilms deposition processes controlled to maintain the desired super-steep retrograde well implant doping profile, photolithographically defining the active device area on the padfilm, retaining a portion of the padfilm over the active area, depositing shallow trench isolation oxide and selectively removing the shallow trench isolation oxide by a process that stops on the underlying padfilm to form a trench isolation region that surrounds the active device area and that extends through the silicon cap layer and into the underlying crystalline silicon substrate.

5. The method of claim 4, further comprising removing the padfilm within the active area to expose the underlying silicon cap layer, forming a gate oxide structure upon the exposed silicon cap layer, and depositing a layer of polycrystalline silicon over the gate oxide structure.

6. The method of claim 5, further comprising doping the polycrystalline silicon layer with a dopant species appropriate for whether the device within the active area is to be an N-type or a P-type field effect transistor, photolithographically defining an upstanding gate stack structure that includes the gate oxide structure and an overlying portion of the doped polycrystalline silicon layer, forming a reoxidation gate stack structure cap and performing a rapid thermal anneal to diffuse the doping in the overlying portion of the polycrystalline silicon layer while not appreciably affecting the desired super-steep retrograde well implant doping profile in the underlying crystalline silicon.

7. The method of claim 6, further comprising forming an offset spacer over the reoxidation gate stack structure cap, implanting extensions, forming a final spacer over the offset spacer, implanting deep source and drain regions, annealing to activate the implanted extensions and source drain regions with a thermal process selected to not appreciably affect the desired super-steep retrograde well implant doping profile in the underlying crystalline silicon, and forming silicide regions over the implanted source and drain regions and over the gate stack structure.

8. The method of claim 7, where the substrate is a silicon-on-insulator substrate, where the ground plane is formed in a crystalline silicon layer that overlies a buried oxide layer, and where the deep source and drain implants create deep source drain junctions that are butted against the layer of buried oxide.

9. The method of claim 7, where substrate is a bulk crystalline silicon substrate, where implanting a ground plane further comprises implanting a higher energy well to provide well isolation, and where the deep source and drain implants create a graded junction at a bottom of the deep source and drain implant region.

10. The method of claim 4, further comprising removing the padfilm within the active area to expose the underlying silicon cap layer, forming a high dielectric constant oxide/metal gate structure upon the exposed silicon cap layer, and depositing a layer of polycrystalline silicon over the high dielectric constant oxide/metal gate structure.

11. The method of claim 10, further comprising doping the polycrystalline silicon layer with a dopant species appropriate for whether the device within the active area is to be an N-type or a P-type field effect transistor, photolithographically defining an upstanding gate stack structure that includes the high dielectric constant oxide/metal gate structure and an overlying portion of the doped polycrystalline silicon layer, forming a nitride gate stack structure cap and performing a rapid thermal anneal to diffuse the doping in the overlying portion of the polycrystalline silicon layer while not appreciably affecting the desired super-steep retrograde well implant doping profile in the underlying crystalline silicon.

12. The method of claim 11, further comprising forming an offset spacer over the nitride gate stack structure cap, implanting extensions, forming a final spacer over the offset spacer, implanting deep source and drain regions, annealing to activate the implanted extensions and source drain regions with a thermal process selected to not appreciably affect the desired super-steep retrograde well implant doping profile in the underlying crystalline silicon, and forming silicide regions over the implanted source and drain regions and over the gate stack structure.

13. The method of claim 12, where the substrate is a bulk crystalline silicon substrate, where implanting a ground plane further comprises implanting a higher energy well to provide well isolation, and where the deep source and drain implants create a graded junction at a bottom of the deep source and drain implant region.

14. A semiconductor structure, comprising:

a substrate comprised of crystalline silicon;

a ground plane in the crystalline silicon adjacent to a surface of the substrate, the ground plane exhibiting a super-steep retrograde well doping profile;

a silicon cap layer over the surface of the substrate, said silicon cap layer being substantially free of faceting; and

a trench isolation region that surrounds an active device area and that is formed through the silicon cap layer and into the underlying crystalline silicon substrate.

15. The semiconductor structure of claim 14, where the substrate is a silicon-on-insulator substrate, and where the ground plane is disposed in a crystalline silicon layer that overlies a buried oxide layer.

16. The semiconductor structure of claim 14, where the substrate is a bulk crystalline silicon substrate, and further comprising a well implanted to provide well isolation.

17. The semiconductor structure of claim 14, where the silicon cap layer is formed with a silicon epitaxy process at a temperature at or below about 700°

C. to maintain the desired super-steep retrograde well doping profile, where the silicon epitaxy process is performed prior to formation of the trench isolation region so that the trench isolation region can be formed through the silicon cap layer.

18. The semiconductor structure of claim 14, further comprising a gate oxide disposed over the silicon cap layer, and a layer of polycrystalline silicon disposed over the gate oxide structure.

19. The semiconductor structure of claim 18, where the polycrystalline silicon layer is doped with a dopant species appropriate for whether a device within the active area is to be an N-type or a P-type field effect transistor, where the gate oxide structure and an overlying portion of the doped polycrystalline silicon layer are disposed within a gate stack structure that is at least partially covered with a reoxidation gate stack structure cap, and further comprising an offset spacer disposed over the reoxidation gate stack structure cap and a final spacer disposed over the offset spacer.

20. The semiconductor structure of claim 14, further comprising a high dielectric constant oxide/metal gate structure disposed over the silicon cap layer, and a layer of polycrystalline silicon disposed over the high dielectric constant oxide/metal gate structure.

21. The semiconductor structure of claim 20, where the polycrystalline silicon layer is doped with a dopant species appropriate for whether a device within the active area is to be an N-type or a P-type field effect transistor, where the high dielectric constant oxide/metal gate structure and an overlying portion of the doped polycrystalline silicon layer are disposed within a gate stack structure that is at least partially covered with a nitride gate stack structure cap, an offset spacer disposed over the nitride gate stack structure cap, and a final spacer disposed over the offset spacer.

22. A complementary metal-oxide-semiconductor super-steep retrograde well field-effect transistor, comprising one of a silicon-on-insulator substrate or a bulk silicon substrate, a ground plane formed in crystalline silicon adjacent to a surface of the substrate, the ground plane having a doping profile that forms the super-steep retrograde well, a silicon cap layer over a surface of the substrate, said silicon cap layer being substantially free of faceting, a trench isolation region that surrounds an active device area and that is formed through the silicon cap layer and into the underlying crystalline silicon of the substrate, one of a gate oxide or a high-K/metal gate structure disposed over the silicon cap layer within the active device area, and a layer of polycrystalline silicon disposed over the gate structure, the polycrystalline silicon layer being doped with a dopant species appropriate for forming one of an N-type or a P-type field-effect transistor.

23. The complementary metal-oxide-semiconductor super-steep retrograde well field-effect transistor of claim 22, where the silicon cap layer is grown with an epitaxial process at a temperature at or below about 700°

C. to maintain a desired super-steep retrograde well doping profile, and where the epitaxial process is performed prior to formation of the trench isolation region so that the trench isolation region can be formed through the silicon cap layer.

24. The complementary metal-oxide-semiconductor super-steep retrograde well field-effect transistor of claim 22, where the gate oxide and an overlying portion of the doped polycrystalline silicon layer are disposed within a gate stack structure that is at least partially covered with a reoxidation cap, and further comprising an offset spacer disposed over the reoxidation cap and a final spacer disposed over the offset spacer.

25. The complementary metal-oxide-semiconductor super-steep retrograde well field-effect transistor of claim 22, where the high-K/metal gate structure and an overlying portion of the doped polycrystalline silicon layer are disposed within a gate stack structure that is at least partially covered with a nitride cap, and further comprising an offset spacer disposed over the nitride cap, and a final spacer disposed over the offset spacer.