FINFET MEMORY DEVICE WITH DUAL SEPARATE GATES AND METHOD OF OPERATION

• US 20090108351A1
• Filed: 10/26/2007
• Published: 04/30/2009
• Est. Priority Date: 10/26/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Wong, Robert C., Zhu, Huilong
• Application Number:
  US11/925,177
• Publication Number:
  US 20090108351A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 with at least two independent gates
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A FinFET device comprises a front gate (FG) and a separate back gate (BG) disposed on opposite sides of the fine. The fin structure may act as a floating body of a volatile memory cell. The front and back gates may be doped with the same or opposite polarity, and may be biased oppositely. A plurality of FinFETs may be connected in a memory array with single column erase, or double column erase capability.

Claims

1. A FinFET device comprising:

a fin structure having two side surfaces, the fin structure having a thickness between its two side surfaces of 20-60 nm;

a layer of oxide disposed on the two side surfaces, the layer of oxide disposed on the two side surfaces of the fin functions as a gate oxide, and has a thickness of 1-3 nm;

a first (“

front”

) gate structure disposed on one side of the fin, with the oxide therebetween;

a second (“

back”

) gate structure disposed on an opposite side of the fin, with the oxide therebetween;

the fin structure comprising a floating body of a volatile memory cell formed using conventional SOI fabrication techniques;

the fin comprising monocrystalline silicon;

the first and second gate structures comprising polycrystalline silicon;

the device is disposed atop a buried oxide (BOX) layer on a substrate,

the BOX layer having a thickness of 500-1000 Å

;

the first gate structure having a first polarity, and the second gate structure having a second polarity which is opposite to the polarity of the first gate structure; and

the first polarity is N+ and the second polarity is P+.

2-20. -20. (canceled)