SEMICONDUCTOR DEVICE

• US 20090108440A1
• Filed: 10/26/2007
• Published: 04/30/2009
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Meyer, Thorsten, Brunnbauer, Markus, Bradl, Stephan, Kastner, Marcus
• Granted Patent: US 7,906,860 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

Claims

1. An arrangement, comprising:

a plurality of semiconductor chips arranged side by side in a spaced apart relationship;

a first material filling at least partly the spacings between adjacent semiconductor chips; and

a second material arranged over the semiconductor chips and the first material,

wherein a coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

2. The arrangement of claim 1, comprising wherein the coefficient of thermal expansion of the first material is larger than the coefficient of thermal expansion of the second material.

3. The arrangement of claim 1, comprising wherein the first material is a foil.

4. The arrangement of claim 1, comprising wherein the first material is made of a curable liquid.

5. The arrangement of claim 1, comprising wherein the first material is one of the group consisting of an epoxy resin, a phenol resin or a thermosetting plastic.

6. The arrangement of claim 1, comprising wherein the first material is filled with a particle-containing filler.

7. The arrangement of claim 6, wherein the filler comprises at least one of the group of glass particles, metal particles or ceramic particles.

8. The arrangement of claim 1, wherein the first material at least partially covers the semiconductor chips.

9. The arrangement of claim 1, comprising wherein the first material separates the plurality of semiconductor chips from the second material.

10. The arrangement of claim 1, comprising wherein a lateral dimension of the arrangement is larger than 20 cm, in particular 30 cm.

11. An arrangement of semiconductor chips, comprising:

a plurality of semiconductor chips arranged side by side in a spaced apart relationship;

a first material filling at least partly the spacings between adjacent semiconductor chips; and

a second material arranged over the semiconductor chips and the first material,

wherein the coefficient of thermal expansion of the first material is in the range of 50 to 100·

10<sup>−

6</sup>/K and the coefficient of thermal expansion of the second material is in the range of 6 to 20·

10<sup>−

6</sup>/K.

12. The arrangement of claim 11, comprising wherein the first material is a foil.

13. The arrangement of claim 11, comprising wherein the first material is made of a curable liquid.

14. The arrangement of claim 11, comprising wherein the first material separates the plurality of semiconductor chips from the second material.

15. The arrangement of claim 11, comprising wherein a lateral dimension of the arrangement is larger than 20 cm.

16. A module, comprising:

a semiconductor chip;

a first material laterally surrounding the semiconductor chip; and

a second material arranged over the semiconductor chip and the first material,

wherein a coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the module in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the module in a plane intersecting the second material.

17. The module of claim 16, comprising wherein the first material is a foil.

18. The module of claim 16, comprising wherein the first material is made of a curable liquid.

19. A method to produce an arrangement of semiconductor chips, comprising:

arranging the semiconductor chips in a spaced apart relationship on a carrier;

filling the spacings between adjacent semiconductor chips with a first material; and

arranging a second material over the semiconductor chips and the first material,

including selecting a coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

20. The method of claim 19, comprising applying the first material as a foil which is laminated onto the carrier mounting the semiconductor chips.

21. The method of claim 20, further comprising:

pressurizing and/or heating the foil in order to assist the filling of the spacings.

22. The method of claim 19, comprising applying the first material as a curable liquid dispensed or printed onto the carrier mounting the semiconductor chips.

23. The method of claim 22, further comprising:

introducing energy to cure the curable liquid prior to arranging the second material.

24. The method of claim 19, further comprising:

separating the carrier from the arrangement of semiconductor chips.

25. A method to produce an arrangement of semiconductor chips, comprising:

arranging the semiconductor chips in a spaced apart relationship on a carrier;

filling the spacings between adjacent semiconductor chips with a first material; and

arranging a second material over the semiconductor chips and the first material,

wherein the coefficient of thermal expansion of the first material is in the range of 50 to 100·

10<sup>−

6</sup>/K and the coefficient of thermal expansion of the second material is in the range of 6 to 20·

10<sup>−

6</sup>/K.