CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME
First Claim
1. A semiconductor chip comprising:
- a silicon substrate;
a transistor in or on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metal layer over said silicon substrate and over said first dielectric layer;
a second metal layer over said first metal layer, wherein said second metal layer is connected to said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening;
a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point; and
a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, and a gold layer over said second electroplated copper layer, wherein said gold layer has a thickness between 1 and 10 micrometers, and wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer.
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Accused Products
Abstract
A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.
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Citations
20 Claims
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1. A semiconductor chip comprising:
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a silicon substrate; a transistor in or on said silicon substrate; a first dielectric layer over said silicon substrate; a first metal layer over said silicon substrate and over said first dielectric layer; a second metal layer over said first metal layer, wherein said second metal layer is connected to said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening; a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point; and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, and a gold layer over said second electroplated copper layer, wherein said gold layer has a thickness between 1 and 10 micrometers, and wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit component comprising:
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a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, wherein said second metal layer is connected to said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer and said first contact point is at a bottom of said first opening, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, and a gold layer over said second electroplated copper layer, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer; and a glass substrate connected to said fourth metal layer of said semiconductor chip. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A circuit component comprising:
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a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, wherein said second metal layer is connected to said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point and said first contact point is at a bottom of said first opening, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, a nickel layer on said second electroplated copper layer, and a gold layer on said nickel layer; and a glass substrate connected to said fourth metal layer of said semiconductor chip. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification