Systems, Circuits and Methods for Extended Range Input Comparison

• US 20090108880A1
• Filed: 10/24/2007
• Published: 04/30/2009
• Est. Priority Date: 10/24/2007
• Status: Abandoned Application

• Current Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Soltanian, Babak
• Application Number:
  US11/877,688
• Publication Number:
  US 20090108880A1
• Time in Patent Office: Days
• US Class Current: 327/52
• CPC Class Codes: H03F 2203/45506 the CSC comprising only one switch
• CPC Class Codes: H03F 2203/45726 the LC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03K 5/2427 using clock signals

Abstract

Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide comparator circuits that include two input stages that each receive a first input and a second input. One of the input stages is sensitive to a difference between the first input and the second input for at least a low common mode, and provides a first output. The other of the input stages is sensitive to a difference between the positive input and the negative input for at least a high common mode, and provides a second output. The comparator circuits further include a regeneration stage that receives the first output and the second output, and provides a comparator output reflecting the difference between the first input and the second input.

Claims

1. A comparator circuit, the comparator circuit comprising:

a first input;

a second input;

a first input stage, wherein the first input stage receives the first input and the second input, wherein the first input stage is sensitive to a difference between the first input and the second input for at least a low common mode, and wherein the first input stage provides a first output synchronized to a prior edge of a clock signal;

a second input stage, wherein the second input stage receives the first input and the second input, wherein the second input stage is sensitive to a difference between the first input and the second input for at least a high common mode, and wherein the second input stage provides a second output synchronized to an edge of an inverted version of the clock signal; and

a regeneration stage, wherein the regeneration stage receives the first output and the second output, and wherein the regeneration stage is operable to provide a comparator output synchronized to a subsequent edge of the clock signal and reflecting the difference between the first input and the second input.

2. The comparator circuit of claim 1, wherein the first input stage includes a differential pair of P-type transistors, wherein the first input is electrically coupled to the gate of one of the P-type transistors of the differential pair, and wherein the second input is electrically coupled to the gate of another of the P-type transistors of the differential pair.

3. The comparator circuit of claim 1, wherein the second input stage includes a differential pair of N-type transistors, wherein the first input is electrically coupled to the gate of one of the N-type transistors of the differential pair, and wherein the second input is electrically coupled to the gate of another of the N-type transistors of the differential pair.

4. The comparator circuit of claim 1, wherein the first input stage includes:

a first N-type transistor;

a second N-type transistor;

a first P-type transistor;

a second P-type transistor; and

wherein the gate of the first N-type transistor and the gate of the second N-type transistor are electrically coupled to the clock signal, wherein the drain of the first N-type transistor is electrically coupled to the drain of the first P-type transistor and the drain of the second N-type transistor is electrically coupled to the drain of the second P-type transistor, and wherein the gate of the first P-type transistor is electrically coupled to the first input and the gate of second P-type transistor is electrically coupled to the second input.

5. The comparator circuit of claim 4, wherein the first input stage further includes:

a third P-type transistor, wherein the source of the first P-type transistor and the source of the second P-type transistor are electrically coupled to the drain of the third P-type transistor, wherein the gate of the third P-type transistor is electrically coupled to the clock signal, wherein the source of the third P-type transistor is electrically coupled to an upper rail, and wherein the source of the first N-type transistor and the source of the second N-type transistor are electrically coupled to a lower rail.

6. The comparator circuit of claim 5, wherein the first output includes a first positive output electrically coupled to the drain of the first P-type transistor and a first negative output electrically coupled to the drain of the second P-type transistor.

7. The comparator circuit of claim 1, wherein the second input stage includes:

a first N-type transistor;

a second N-type transistor;

a first P-type transistor;

a second P-type transistor; and

wherein the gate of the first P-type transistor and the gate of the second P-type transistor are electrically coupled to an inverted version of the clock signal, wherein the drain of the first P-type transistor is electrically coupled to the drain of the first N-type transistor and the drain of the second P-type transistor is electrically coupled to the drain of the second N-type transistor, and wherein the gate of the first N-type transistor is electrically coupled to the first input and the gate of second N-type transistor is electrically coupled to the second input.

8. The comparator circuit of claim 7, wherein the second input stage further includes:

a third N-type transistor, wherein the source of the first N-type transistor and the source of the second N-type transistor are electrically coupled to the drain of the third N-type transistor, wherein the gate of the third N-type transistor is electrically coupled to the clock signal, wherein the source of the third N-type transistor is electrically coupled to a lower rail, and

wherein the source of the first P-type transistor and the source of the second P-type transistor are electrically coupled to an upper rail.

9. The comparator circuit of claim 8, wherein the second output includes a second positive output electrically coupled to the drain of the first P-type transistor and a second negative output electrically coupled to the drain of the second P-type transistor.

10. The comparator circuit of claim 1, wherein the first output includes a first positive output and a first negative output, wherein the second output includes a second positive output and a second negative output, and wherein the regeneration stage includes:

a first, second, third and fourth N-type transistors;

a first, second, third, fourth and fifth P-type transistors;

wherein the gate of the first P-type transistor is electrically coupled to the first negative output, wherein the gate of the fourth P-type transistor is electrically coupled to the first positive output;

wherein the gate of the first N-type transistor is electrically coupled to the second negative output, wherein the gate of the fourth N-type transistor is electrically coupled to the second positive output;

wherein the gate of the second P-type transistor is electrically coupled to the gate of the second N-type transistor;

wherein the gate of the third P-type transistor is electrically coupled to the gate of the third N-type transistor;

wherein the drains of the first P-type transistor and the second P-type transistor are electrically coupled to the drains of the first N-type transistor and the second N-type transistor;

wherein the drains of the third P-type transistor and the fourth P-type transistor are electrically coupled to the drains of the third N-type transistor and the fourth N-type transistor;

wherein the comparator output is electrically coupled to nodes selected from a group consisting of;

the gate of the second P-type transistor and the drain of the third P-type transistor, and the gate of the third P-type transistor and the drain of the second P-type transistor; and

wherein the source of the fifth P-type transistor is electrically coupled to an upper rail, wherein the drain of the fifth P-type transistor is electrically coupled to the source of the first P-type transistor, the second P-type transistor, the third P-type transistor and the fourth P-type transistor; and

wherein the gate of the fifth P-type transistor is electrically coupled to the clock signal.

11. A mixed signal integrated circuit, the mixed signal integrated circuit comprising:

a differential analog input signal, wherein the differential analog input signal includes a first signal and a second signal;

a multiple input stage comparator, wherein the multiple input stage comparator includes;

a first input stage, wherein the first input stage receives the first signal and the second signal, wherein the first input stage is sensitive to a difference between the first signal and the second signal for at least a low common mode, and wherein the first input stage provides a first positive output and a first negative output each synchronized to a prior edge of a clock signal;

a second input stage, wherein the second input stage receives the first signal and the second signal, wherein the second input stage is sensitive to a difference between the first signal and the second signal for at least a high common mode, and wherein the second input stage provides a second positive output and a second negative output each synchronized to an edge of an inverted version of the clock signal; and

a regeneration stage, wherein the regeneration stage receives the first positive output, the first negative output, the second positive output and the second negative output, and wherein the regeneration stage is operable to provide a comparator output synchronized to a subsequent edge of the clock signal and reflecting a relative difference of the first signal and the second signal.

12. The circuit of claim 11, wherein the comparator output includes a positive comparator output and a negative comparator output, and wherein the positive comparator output and the negative comparator output are selected from a group consisting of:

approximately an upper rail and approximately a lower rail; and

approximately the lower rail and approximately the upper rail.

13. The circuit of claim 11, wherein the comparator output is a digital output, and wherein the digital output switches between approximately an upper rail and a lower rail.

14. The circuit of claim 11, wherein:

the first input stage includes;

a first N-type transistor;

a second N-type transistor;

a first P-type transistor;

a second P-type transistor; and

wherein the gate of the first N-type transistor and the gate of the second N-type transistor are electrically coupled to the clock signal, wherein the drain of the first N-type transistor is electrically coupled to the drain of the first P-type transistor and the drain of the second N-type transistor is electrically coupled to the drain of the second P-type transistor, and wherein the gate of the first P-type transistor is electrically coupled to the first signal and the gate of second P-type transistor is electrically coupled to the second signal;

the second input stage includes;

a third N-type transistor;

a fourth N-type transistor;

a third P-type transistor;

a fourth P-type transistor; and

wherein the gate of the third P-type transistor and the gate of the fourth P-type transistor are electrically coupled to an inverted version of the clock signal, wherein the drain of the third P-type transistor is electrically coupled to the drain of the third N-type transistor and the drain of the fourth P-type transistor is electrically coupled to the drain of the fourth N-type transistor, and wherein the gate of the third N-type transistor is electrically coupled to the first signal and the gate of fourth N-type transistor is electrically coupled to the second signal.

15. The circuit of claim 14, wherein the regeneration stage includes:

a fifth, sixth, seventh and eighth N-type transistors;

a fifth, sixth, seventh, eighth and ninth P-type transistors;

wherein the gate of the fifth P-type transistor is electrically coupled to the first negative output, wherein the gate of the eighth P-type transistor is electrically coupled to the first positive output;

wherein the gate of the fifth N-type transistor is electrically coupled to the second negative output, wherein the gate of the eighth N-type transistor is electrically coupled to the second positive output;

wherein the gate of the sixth P-type transistor is electrically coupled to the gate of the sixth N-type transistor;

wherein the gate of the seventh P-type transistor is electrically coupled to the gate of the seventh N-type transistor;

wherein the drains of the fifth P-type transistor and the sixth P-type transistor are electrically coupled to the drains of the fifth N-type transistor and the sixth N-type transistor;

wherein the drains of the seventh P-type transistor and the eighth P-type transistor are electrically coupled to the drains of the seventh N-type transistor and the eighth N-type transistor;

wherein the comparator output is electrically coupled to nodes selected from a group consisting of;

the gate of the sixth P-type transistor and the drain of the seventh P-type transistor, and the gate of the seventh P-type transistor and the drain of the sixth P-type transistor; and

wherein the source of the fifth P-type transistor is electrically coupled to an upper rail, wherein the drain of the fifth P-type transistor is electrically coupled to the source of the first P-type transistor, the second P-type transistor, the third P-type transistor and the fourth P-type transistor; and

wherein the gate of the fifth P-type transistor is electrically coupled to the clock signal.

16. An electronic device, the electronic device comprising:

a circuit performing an electronic function, wherein the circuit includes at least one multiple input stage comparator circuit including;

a first input and a second input;

a first input stage, wherein the first input stage receives the first input and the second input, wherein the first input stage is sensitive to a difference between the first input and the second input for at least a low common mode, and wherein the first input stage provides a first positive output and a first negative output each synchronized to a prior edge of a clock signal;

a second input stage, wherein the second input stage receives the first input and the second input, wherein the second input stage is sensitive to a difference between the first input and the second input for at least a high common mode, and wherein the second input stage provides a second positive output and a second negative output each synchronized to an edge of an inverted version of the clock signal; and

a regeneration stage, wherein the regeneration stage receives the first positive output, the first negative output, the second positive output and the second negative output, and wherein the regeneration stage is operable to provide a comparator output synchronized to a subsequent edge of the clock signal and reflecting a relative difference of the first input and the second input.

17. The electronic device of claim 16, wherein the circuit is a mixed signal circuit, wherein the first input and the second input together form an analog differential pair, and wherein the comparator output is a digital output.

18. The electronic device of claim 16, wherein the first input stage includes a first differential pair of P-type transistors;

wherein the first input is electrically coupled to the gate of a first of the P-type transistors of the first differential pair, wherein the second input is electrically coupled to the gate of a second of the P-type transistors of the first differential pair;

wherein the first positive output is electrically coupled to the drain of the first of the P-type transistors and the first negative output is electrically coupled to the drain of the second of the P-type transistors;

wherein the second input stage includes a second differential pair of N-type transistors;

wherein the first input is electrically coupled to the gate of a first of the N-type transistors of the second differential pair, wherein the second input is electrically coupled to the gate of a second of the N-type transistors of the second differential pair; and

wherein the second positive output is electrically coupled to the drain of the first of the N-type transistors and the second negative output is electrically coupled to the drain of the second of the N-type transistors.

19. The electronic device of claim 16, wherein the electronic device is selected from a group consisting of:

a communication device, a hard disk drive, an audio player, and a video player.

20. The electronic device of claim 16, wherein the electronic function is selected from a group consisting of:

a communication function, a data storage function, a audio record function, an audio play function, a video record function, and a video play function.