Systems, Circuits and Methods for Extended Range Input Comparison
First Claim
1. A comparator circuit, the comparator circuit comprising:
- a first input;
a second input;
a first input stage, wherein the first input stage receives the first input and the second input, wherein the first input stage is sensitive to a difference between the first input and the second input for at least a low common mode, and wherein the first input stage provides a first output synchronized to a prior edge of a clock signal;
a second input stage, wherein the second input stage receives the first input and the second input, wherein the second input stage is sensitive to a difference between the first input and the second input for at least a high common mode, and wherein the second input stage provides a second output synchronized to an edge of an inverted version of the clock signal; and
a regeneration stage, wherein the regeneration stage receives the first output and the second output, and wherein the regeneration stage is operable to provide a comparator output synchronized to a subsequent edge of the clock signal and reflecting the difference between the first input and the second input.
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Abstract
Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide comparator circuits that include two input stages that each receive a first input and a second input. One of the input stages is sensitive to a difference between the first input and the second input for at least a low common mode, and provides a first output. The other of the input stages is sensitive to a difference between the positive input and the negative input for at least a high common mode, and provides a second output. The comparator circuits further include a regeneration stage that receives the first output and the second output, and provides a comparator output reflecting the difference between the first input and the second input.
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Citations
20 Claims
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1. A comparator circuit, the comparator circuit comprising:
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a first input; a second input; a first input stage, wherein the first input stage receives the first input and the second input, wherein the first input stage is sensitive to a difference between the first input and the second input for at least a low common mode, and wherein the first input stage provides a first output synchronized to a prior edge of a clock signal; a second input stage, wherein the second input stage receives the first input and the second input, wherein the second input stage is sensitive to a difference between the first input and the second input for at least a high common mode, and wherein the second input stage provides a second output synchronized to an edge of an inverted version of the clock signal; and a regeneration stage, wherein the regeneration stage receives the first output and the second output, and wherein the regeneration stage is operable to provide a comparator output synchronized to a subsequent edge of the clock signal and reflecting the difference between the first input and the second input. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A mixed signal integrated circuit, the mixed signal integrated circuit comprising:
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a differential analog input signal, wherein the differential analog input signal includes a first signal and a second signal; a multiple input stage comparator, wherein the multiple input stage comparator includes; a first input stage, wherein the first input stage receives the first signal and the second signal, wherein the first input stage is sensitive to a difference between the first signal and the second signal for at least a low common mode, and wherein the first input stage provides a first positive output and a first negative output each synchronized to a prior edge of a clock signal; a second input stage, wherein the second input stage receives the first signal and the second signal, wherein the second input stage is sensitive to a difference between the first signal and the second signal for at least a high common mode, and wherein the second input stage provides a second positive output and a second negative output each synchronized to an edge of an inverted version of the clock signal; and a regeneration stage, wherein the regeneration stage receives the first positive output, the first negative output, the second positive output and the second negative output, and wherein the regeneration stage is operable to provide a comparator output synchronized to a subsequent edge of the clock signal and reflecting a relative difference of the first signal and the second signal. - View Dependent Claims (12, 13, 14, 15)
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16. An electronic device, the electronic device comprising:
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a circuit performing an electronic function, wherein the circuit includes at least one multiple input stage comparator circuit including; a first input and a second input; a first input stage, wherein the first input stage receives the first input and the second input, wherein the first input stage is sensitive to a difference between the first input and the second input for at least a low common mode, and wherein the first input stage provides a first positive output and a first negative output each synchronized to a prior edge of a clock signal; a second input stage, wherein the second input stage receives the first input and the second input, wherein the second input stage is sensitive to a difference between the first input and the second input for at least a high common mode, and wherein the second input stage provides a second positive output and a second negative output each synchronized to an edge of an inverted version of the clock signal; and a regeneration stage, wherein the regeneration stage receives the first positive output, the first negative output, the second positive output and the second negative output, and wherein the regeneration stage is operable to provide a comparator output synchronized to a subsequent edge of the clock signal and reflecting a relative difference of the first input and the second input. - View Dependent Claims (17, 18, 19, 20)
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Specification