ARRAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME

• US 20090109384A1
• Filed: 06/13/2008
• Published: 04/30/2009
• Est. Priority Date: 10/29/2007
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Heo, Jeong-Uk, Kim, Su-Jeong, Kim, Kwang-Hyun, Jung, Ji-Yoon, Lee, Nam-Seok
• Application Number:
  US12/138,929
• Publication Number:
  US 20090109384A1
• Time in Patent Office: Days
• US Class Current: 349/106
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

An array substrate includes: a gate line, a data line crossing disposed substantially perpendicular to the gate line, a first switching element being electrically connected to the gate line and the data line, a pixel electrode being electrically connected to the first switching element to be formed in a pixel area, the pixel electrode having including an opening pattern, and a light-blocking wiring formed disposed in correspondence with the opening pattern is formed, the light-blocking wiring including a convex-concave pattern.

Claims

1. An array substrate comprising:

a gate line;

a data line crossing the gate line;

a first switching element electrically connected to the gate line and the data line;

a pixel electrode electrically connected to the first switching element, the pixel electrode including an opening pattern; and

a light-blocking wiring disposed in correspondence with the opening pattern, the light-blocking wiring including a convex-concave pattern.

2. The array substrate of claim 1, wherein the opening pattern and the light-blocking wiring are disposed in a diagonal line direction with respect to the gate line, when viewed from a plan view.

3. The array substrate of claim 2, wherein a shape of the opening pattern is substantially equal to that of the light-blocking wiring.

4. The array substrate of claim 2, wherein a width of the opening pattern is about 3.5 μ

m to about 10 μ

m.

5. The array substrate of claim 2, wherein the convex-concave pattern is disposed on at least one of a first edge portion of the light-blocking wiring and a second edge portion of the light-blocking wiring substantially opposite to the first edge portion, when viewed from a plan view.

6. The array substrate of claim 5, wherein the convex-concave pattern comprises a unit shape having a convex shape extending away from at least one of the first edge portion of the light-blocking wiring and the second edge portion of the light-blocking wiring substantially opposite to the first edge portion, when viewed from a plan view.

7. The array substrate of claim 5, wherein the convex-concave pattern comprises a unit shape having a concave shape recessed inward from at least one of the first edge portion of the light-blocking wiring and the second edge portion of the light-blocking wiring substantially opposite to the first edge portion, when viewed from a top plan view.

8. The array substrate of claim 5, wherein the convex-concave pattern comprises a unit shape having a first slant portion and a second slant portion disposed at an angle to each other, and

a crossing portion wherein the first slant portion and the second slant portion intersect has one of an angled shape and a rounded shape.

9. The array substrate of claim 8, wherein the angle between the first slant portion and the second slant portion is about 60 degrees to about 120 degrees.

10. The array substrate of claim 8, wherein a length of each of the first and second slant portions is about 5 μ

m to about 10 μ

m.

11. The array substrate of claim 8, wherein a width of a straight portion of the light-blocking wiring excluding the convex-concave pattern is about 2 μ

m to about 4 μ

m.

12. The array substrate of claim 2, further comprising:

a storage line disposed such that the pixel electrode overlaps at least a portion thereof, the storage line being electrically connected to the light-blocking wiring.

13. The array substrate of claim 12, wherein the pixel electrode comprises a first sub-electrode and a second sub-electrode spaced apart from the first sub-electrode by the opening pattern, and wherein the first sub-electrode is formed to substantially surround the second sub-electrode on at least three sides.

14. The array substrate of claim 13, wherein an edge portion of the light-blocking wiring contacts at least one of an edge portion of the first sub-electrode and an edge portion of the second sub-electrode.

15. The array substrate of claim 13, wherein the light-blocking wiring further comprises an overlapping portion which overlaps at least one of the first sub-electrode and the second sub-electrode.

16. The array substrate of claim 13, wherein the first switching element comprises:

a dual source electrode which overlaps the gate line, the dual source electrode being connected to the data line;

a first drain electrode spaced apart from the dual source electrode, the first drain electrode contacting the first sub-electrode; and

a second drain electrode spaced apart from the dual electrode, the second drain electrode contacting the second sub-electrode.

17. The array substrate of claim 16, further comprising:

a second switching element including a source electrode which contacts the second sub-electrode and a third drain electrode which is overlapped by the first sub-electrode.

18. An array substrate comprising:

first and second gate lines disposed on a base substrate;

a data line crossing the first and second gate lines;

a pixel electrode, including a first sub-electrode and a second sub-electrode spaced apart from the first sub-electrode by an opening pattern formed in a diagonal direction with respect to the first and second gate lines;

a storage line overlapped by the first and second sub-electrodes, wherein sections of the storage line are disposed substantially in parallel with one of the first and second gate lines and the data line;

a light-blocking wiring disposed in correspondence with the opening pattern, wherein the light-blocking wiring is electrically connected to the storage line, the light-blocking wiring including a concave-convex pattern;

a dual switching element electrically connected to the first gate line and the data line, the dual switching element including a first drain electrode which contacts the first sub-electrode and a second drain electrode which contacts the second sub-electrode; and

a switching element electrically connected to the second gate line and the data line, the switching element including a source electrode which contacts the second sub-electrode and a third drain electrode which is overlapped by the first sub-electrode.

19. A display panel comprising:

an array substrate including;

a switching element electrically connected to a gate line disposed on a base substrate and a data line disposed on the base substrate;

a pixel electrode electrically connected to the switching element, the pixel electrode having a first opening pattern formed thereon in a diagonal line with respect to the gate line; and

a light-blocking wiring disposed in correspondence with the opening pattern, the light-blocking wiring including a concave-convex pattern having a first slant part and a second slant part disposed at an angle to each other; and

an opposite substrate disposed substantially opposite to the array substrate, the opposite substrate including a common electrode having a second opening pattern formed thereon, wherein the second opening pattern defines a liquid crystal domain with the first opening pattern.

20. The display panel of claim 19, wherein the angle between the first slant portion and the second slant portion is about 60 degrees to about 120 degrees.

21. The display panel of claim 20, further comprising:

a first polarizing plate attached to the array substrate, the first polarizing plate having a first polarizing axis; and

a second polarizing plate attached to the opposite substrate, the second polarizing plate having a second polarizing axis substantially perpendicular to the first polarizing axis,

wherein the first slant portion is disposed at an angle of about 0 degrees to about 45 degrees with respect to the first polarizing axis, and the second slant portion is disposed at an angle of about 0 degree to about 45 degrees with respect to the second polarizing axis.