SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING

• US 20090109750A1
• Filed: 10/23/2008
• Published: 04/30/2009
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 8,059,459 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping latter for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory, as non-volatile memory when power to the device is interrupted.

Claims

1. A method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:

reading and storing data to the floating bodies as volatile memory, while power is applied to the device;

transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating bodies, when power to the device is interrupted; and

storing the data in the floating gates or trapping layers as non-volatile memory.

2. The method of claim 1, further comprising:

transferring the data stored in the floating gates or trapping layers, by a parallel, non-algorithmic restore process, to the floating bodies corresponding to the floating gates or trapping layers, when power is restored to the cell;

and storing the data in the floating bodies as volatile memory.

3. The method of claim 1, further comprising initializing the floating gates or trapping layers, to each have the same predetermined state prior to the transferring.

4. The method of claim 3, wherein the predetermined state comprises a positive charge.

5. The method of claim 1, wherein the data transferred is stored in the floating gates or trapping layers with charges that are complementary to charges of the floating bodies when storing the data.

6. The method of claim 2, further comprising restoring the floating gates or trapping layers to a predetermined charge state after the restore process.

7. The method of claim 2, further comprising writing a predetermined state to the floating bodies prior to the transferring the data stored in the floating gates or trapping layers to the floating bodies.

8. The method of claim 7, wherein the predetermined state is state “

0”

.

9. A semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

10. The device of claim 9, wherein data is transferred from the volatile memory to the non-volatile memory by a parallel, non-algorithmic mechanism.

11. The device of claim 9, wherein the device is configured to transfer data stored in non-volatile memory to store the data in the volatile memoir, when power is restored to the device.

12. The device of claim 11, wherein the data is transferred from the non-volatile memory, to the volatile memory by a parallel, non-algorithmic mechanism.

13. The device of claim 9, wherein the memory, cells function as multi-level cells.

14. A memory string comprising a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising:

a floating substrate region having a first conductivity type;

first and second regions each having a second conductivity type and interfacing with the floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory;

a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer;

the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell;

a control gate positioned adjacent the floating gate or trapping layer; and

a second insulating layer between the floating gate or trapping layer and the control gate.

15. The memory string of claim 14, wherein the semiconductor memory cells are substantially planar.

16. The memory string of claim 14, wherein the semiconductor memory cells comprise three-dimensional cells, each having a fin extending from a substrate.

17. The memory string of claim 14, further comprising a string selection transistor connected to one end of the plurality of semiconductor memory cells connected in series, and a ground selection transistor connected to an opposite end the plurality of semiconductor memory cells connected in series.

18. The memory, string of claim 14, wherein the semiconductor memory cells function as multi-level cells.

19. A memory cell device comprising a plurality of memory strings assembled to form a grid of semiconductor memory cells each said memory string comprising a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising:

a floating substrate region having a first conductivity type;

first and second regions each having a second conductivity type and interfacing with said floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory;

a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer;

the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell;

a control gate positioned adjacent the floating gate or trapping layer; and

a second insulating later between the floating gate or trapping layer and the control gate.

20. The memory cell device of claim 19, wherein said memory strings form columns of the grid.

21. The memory cell device of claim 20, wherein said columns are insulated from one another by insulating members placed between said columns.

22. The memory cell device of claim 19, wherein the semiconductor memory cells function as multi-level cells.