MEMORY HAVING CIRCUITRY CONTROLLING THE VOLTAGE DIFFERENTIAL BETWEEN THE WORD LINE AND ARRAY SUPPLY VOLTAGE

• US 20090109785A1
• Filed: 10/31/2007
• Published: 04/30/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W., Marshall, Andrew
• Granted Patent: US 7,907,456 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage differential generating circuit is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage.

Claims

1. An integrated circuit (IC), comprising:

at least one memory array comprising a plurality of memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells, and

voltage differential generating circuitry operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein said differential is a function of said array supply voltage.

2. The IC of claim 1, wherein said differential is also a function of a process related device parameter or a temperature during operation of said IC.

3. The IC of claim 2, wherein said process related device parameter is selected from Vtn, Vtp, gm, Idsat, or Idlin.

4. The IC of claim 1, where said supply voltage comprises a high supply for said array (VDDM).

5. The IC of claim 1, wherein said memory comprises an SRAM.

6. The IC of claim 1, wherein said memory comprises an FeRAM or an MRAM.

7. The IC of claim 1, further comprising trend selection storage circuitry on said IC coupled to said voltage differential generating circuitry operable to select a trend which relates said VWL as a function of said array supply voltage from a plurality of different ones of said trends.

8. The IC of claim 7, wherein said trend selection storage circuitry is programmable.

9. The IC of claim 1, further comprising trend selection circuitry coupled to said voltage differential generating circuitry.

10. The IC of claim 9, wherein said trend selection circuitry consists of a single global trend selection circuit.

11. The IC claim 9, wherein said trend selection circuitry comprises a plurality of local trend selection circuits.

12. The IC of claim 1, wherein said voltage differential generating circuitry consists of a single global voltage differential generating circuit.

13. The IC of claim 1, wherein said voltage differential generating circuitry comprises a plurality of independent local voltage differential generating circuits.

14. The IC of claim 13, wherein said plurality of local voltage differential circuits include a MOS strength or a parameter related thereto as an input.

15. The IC of claim 14, wherein said plurality of local voltage differential generating circuits include a differential input amplifier, wherein a gain of said amplifier is determined by said MOS strength parameter or said parameter related thereto.

16. The IC of claim 4, wherein said voltage differential generating circuitry is operable to set VWL=VDDM for VDDM less than a voltage level and VWL<

VDDM for VDDM above said voltage level.

17. The IC of claim 16, wherein said VWL is clamped at a level above said voltage level.

18. An integrated circuit (IC), comprising:

at least one memory array comprising a plurality of SRAM memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells;

said memory cells each including first and second cross-coupled inverters comprising PMOS loads and NMOS pull up devices, said first inverter having a first latch node and said second inverter having a second latch node; and

one or more NMOS pass transistor coupled to said first latch node and to said second latch node, one of said word lines being connected to a gate of said pass transistor and one of said bit lines being connected to a source or drain of said pass transistor;

a low supply voltage for said array (VSSM) coupled to a low voltage supply terminal of said cross-coupled inverters, and a high voltage supply for said array (VDDM) coupled to a high voltage supply terminal of said cross-coupled inverters;

at least one voltage differential determining circuit operable for dynamically controlling a voltage differential between said VDDM and a word line voltage (VWL) coupled to said plurality of word lines, wherein said voltage differential is based on said VDDM and at least one process related parameter associated with said array.

19. The IC of claim 18, wherein said at least one voltage differential determining circuit comprises plurality of voltage differential determining circuits.

20. A method of operating a integrated circuit comprising at least one memory array, said memory array comprising a plurality of memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells, the method comprising the step of:

automatically setting a voltage differential between a supply voltage for said array and a word line voltage (VWL) coupled to said plurality of word lines based on at least said supply voltage.

21. The method of claim 20, further comprising the step of selecting a trend from of a plurality trends which relate said VWL as a function of said array supply voltage, wherein said VWL is based on said trend and said supply voltage.

22. The method of claim 21, wherein said selecting consists of a single global selection for said IC.

23. The method of claim 20, wherein said setting step comprises dynamically setting, wherein said voltage differential is automatically updated during operation of said IC.

24. The method of claim 20, wherein said voltage differential comprises VWL=VDDM for VDDM less than a voltage level and VWL<

VDDM for VDDM greater than said voltage level, wherein said VDDM comprises a high voltage supply for said array.

25. The method of claim 20, wherein said voltage differential comprises VWL>

VDDM for VDDM less than a voltage level and VWL<

VDDM for VDDM greater than the voltage level, wherein said VDDM comprises a high voltage supply for said array.