MEMORY HAVING CIRCUITRY CONTROLLING THE VOLTAGE DIFFERENTIAL BETWEEN THE WORD LINE AND ARRAY SUPPLY VOLTAGE
First Claim
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1. An integrated circuit (IC), comprising:
- at least one memory array comprising a plurality of memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells, andvoltage differential generating circuitry operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein said differential is a function of said array supply voltage.
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Abstract
An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage differential generating circuit is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage.
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Citations
25 Claims
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1. An integrated circuit (IC), comprising:
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at least one memory array comprising a plurality of memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells, and voltage differential generating circuitry operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein said differential is a function of said array supply voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An integrated circuit (IC), comprising:
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at least one memory array comprising a plurality of SRAM memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells; said memory cells each including first and second cross-coupled inverters comprising PMOS loads and NMOS pull up devices, said first inverter having a first latch node and said second inverter having a second latch node; and
one or more NMOS pass transistor coupled to said first latch node and to said second latch node, one of said word lines being connected to a gate of said pass transistor and one of said bit lines being connected to a source or drain of said pass transistor;a low supply voltage for said array (VSSM) coupled to a low voltage supply terminal of said cross-coupled inverters, and a high voltage supply for said array (VDDM) coupled to a high voltage supply terminal of said cross-coupled inverters; at least one voltage differential determining circuit operable for dynamically controlling a voltage differential between said VDDM and a word line voltage (VWL) coupled to said plurality of word lines, wherein said voltage differential is based on said VDDM and at least one process related parameter associated with said array. - View Dependent Claims (19)
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20. A method of operating a integrated circuit comprising at least one memory array, said memory array comprising a plurality of memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells, the method comprising the step of:
automatically setting a voltage differential between a supply voltage for said array and a word line voltage (VWL) coupled to said plurality of word lines based on at least said supply voltage. - View Dependent Claims (21, 22, 23, 24, 25)
Specification