METHOD AND APPARATUS FOR DATA RECOVERY

• US 20090110115A1
• Filed: 01/05/2009
• Published: 04/30/2009
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: DALLY, WILLIAM J.
• Granted Patent: US 8,233,567 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A method for recovering data includes oversampling an input data signal to provide sample sets, and storing a plurality of sample sets in addressable memory. The sample sets are processed, using sequential logic to make determinations of respective samples suitable for use in data recovery from corresponding sample sets. One function applied for the determination, includes taking a first mean transition position in a first group of sample sets, taking a second mean transition position in a second group of sample sets, computing a slope value for change in transition position, and making the determination based on the order of the plurality of samples, the first and second means, and the slope. The determined samples are obtained and data recovery is achieved. Sample sets can be modified according to equalization functions. Other modifications include encoding the sample sets for data compression.

Claims

1. A method for recovering data from a data signal carrying data symbols, comprising:

oversampling the data signal with a receiver to provide sample sets;

storing a plurality of the sample sets in memory;

determining data symbol transition times by sequentially processing the plurality of the sample sets; and

using the determined data symbol transition times and the sample sets in the memory to determine the data symbols from the stored data samples.

2. The method of claim 1, wherein the determined data symbol transition times identify respective subsets for particular sample sets in the plurality of sample sets, the respective subsets including one or more samples suitable for use in data recovery;

and

after storing the plurality of sample sets in the memory, reading out the respective subset for a particular sample set in the plurality of sample sets from the memory.

3. The method of claim 1, including oversampling the data signal with reference to phase of a receiver clock.

4. The method of claim 3, wherein the data signal is plesiochronous relative to the receiver clock.

5. The method of claim 1, wherein said processing includes computing a pattern of change in the plurality of sample sets, and applying the pattern to make said determination.

6. The method of claim 1, wherein said determination is a function of the samples in more than two sample sets, and of an order of the sample sets.

7. The method of claim 1, including modifying at least one sample set in the plurality of sample sets based on an equalization function.

8. The method of claim 1, wherein the plurality of sample sets consists of 6 or more samples per data symbol.

9. The method of claim 1, wherein the plurality of sample sets consists of more than 100 samples.

10. An integrated circuit, comprising:

an input adapted for connection to a data signal carrying data symbols;

a memory;

oversampling circuitry coupled to the input and to the memory, which oversamples the data signal to provide a plurality of sample sets, and which stores the plurality of sample sets in the memory;

a sequential processor responsive to a sequential logic clock arranged to make determinations of data symbol transition times for more than two sample sets in the plurality of sample sets as a function of at least two of the sample sets in the plurality; and

logic to use the determined data symbol transition times and the sample sets in the memory to determine data symbols from the stored data samples.

11. The integrated circuit of claim 10, wherein the determined data symbol transition times identify respective subsets for particular sample sets in the plurality of sample sets, the respective subsets including one or more samples suitable for use in data recovery;

and

logic to read out the respective subset for a particular sample set in the plurality of sample sets from the memory after the plurality of sample sets is stored in the memory.

12. The integrated circuit of claim 10, wherein the oversampling circuitry oversamples the data signal with reference to phase of a receiver clock.

13. The integrated circuit of claim 11, wherein the data signal is plesiochronous relative to the receiver clock.

14. The integrated circuit of claim 10, wherein said sequential processor includes logic to compute a pattern of change in the plurality of sample sets, and to apply the pattern to make said determination.

15. The integrated circuit of claim 10, wherein said determination is a function of the samples in more than two sample sets, and of an order of the sample sets.

16. The integrated circuit of claim 10, including a sample set modifier that modifies at least one sample set in the plurality of sample sets based on an equalization function.

17. The integrated circuit of claim 10, wherein the sample sets consist of 6 or more samples per data symbol.

18. The integrated circuit of claim 10, wherein the plurality of sample sets consist of more than 100 samples.

19. An apparatus including a receiver having an input for a data signal, the receiver comprising:

a memory;

oversampling circuitry coupled to the input and to the memory, which oversamples the data signal to provide a plurality of sample sets, the sample sets including samples of the respective data symbols, and which stores the plurality of sample sets in the memory;

a sequential processor responsive to a sequential logic clock arranged to make, determinations of data symbol transition times for more than two sample sets in the plurality of sample sets as a function of at least two of the sample sets in the plurality; and

logic to use the determined data symbol transition times and the sample sets in the memory to determine the respective data symbols from the stored data samples.

20. An apparatus, comprising:

a switch, having a plurality of inputs and at least one output, which switches without re-clocking to provide a data signal on the at least one output;

a receiver, coupled to the at least one output of the switch, the receiver including

a memory;

oversampling circuitry coupled to the input and to the memory, which oversamples the data signal to provide a plurality of sample sets, the sample sets including samples of the respective data symbols, and which stores the plurality of sample sets in the memory;

a sequential processor responsive to a sequential logic clock arranged to make, determinations of data symbol transition times for more than two sample sets in the plurality of sample sets as a function of at least two of the sample sets in the plurality; and

logic to use the determined data symbol transition times and the sample sets in the memory to determine the respective data symbols from the stored data samples.

21. An apparatus for recovering data from a data signal, comprising:

means for oversampling the data signal with a receiver to provide sample sets, the sample sets including samples of respective data symbols;

means for storing a plurality of the sample sets in memory;

means for determining data symbol transition times by sequentially processing the plurality of the sample sets; and

means for using the determined data symbol transition times and the sample sets in the memory to determine the respective data symbols from the stored data samples.

22. A method for recovering data from a data signal, comprising:

oversampling the data signal with reference to a sample parameter to provide sample sets, the sample sets including samples of the respective data symbols;

modifying at least one sample set;

storing a plurality of sample sets in memory, including the at least one modified sample set;

processing more than one sample set in the plurality of sample sets to make determinations of respective subsets for particular sample sets in the plurality of sample sets, the respective subsets including one or more samples suitable for use in data recovery; and

after storing the plurality of sample sets in the memory, reading out the respective subset for the at least one modified sample set in the plurality of sample sets from the memory.

23. A method for recovering data from a data signal, comprising:

oversampling the data signal with reference to a sample parameter to provide sample sets, the sample sets including samples of the respective data symbols;

modifying at least one sample set according to an equalization function;

storing a plurality of sample sets in memory, including the at least one modified sample set;

processing more than one sample set in the plurality of sample sets to make the determinations of respective subsets for particular sample sets in the plurality of sample sets, the respective subsets including one or more samples suitable for use in data recovery; and

after storing the plurality of sample sets in the memory, reading out the respective subset for the at least one modified sample set in the plurality of sample sets from the memory.

24. A method for recovering data from a data signal, comprising:

oversampling the data signal with reference to a sample parameter to provide sample sets, the sample sets including samples of the respective data symbols;

modifying at least one sample set for data compression;

storing a plurality of sample sets in memory, including the at least one modified sample set;

processing more than one sample set in the plurality of sample sets to make determinations of respective subsets for particular sample sets in the plurality of sample sets, the respective subsets including one or more samples suitable for use in data recovery; and

after storing the plurality of sample sets in the memory, reading out the respective subset for the at least one modified sample set in the plurality of sample sets from the memory.

25. An apparatus comprising:

a transmitter to transmit a data signal carrying data symbols;

a receiver to receive the data signal including a memory and oversampling circuitry coupled to the input and to the memory, which oversamples the data signal to provide a plurality of sample sets, and which stores the plurality of sample sets in the memory;

a sequential processor responsive to a sequential logic clock arranged to make, determinations of data symbol transition times for more than two sample sets in the plurality of sample sets as a function of at least two of the sample sets in the plurality; and

logic to use the determined data symbol transition times and the sample sets in the memory to determine the data symbols from the stored data samples.