METHOD FOR INTEGRATING NVM CIRCUITRY WITH LOGIC CIRCUITRY
First Claim
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1. A method comprising:
- providing a substrate having a first defined area and a second defined area that is electrically separated from first defined area;
providing a first layer of gate material overlying the substrate in both the first defined area and the second defined area;
providing multiple adjoining sacrificial layers overlying the first layer of gate material;
using the multiple adjoining sacrificial layers to form transistor control electrodes in the first defined area wherein at least one of the adjoining sacrificial layers is not completely removed;
using at least one of the adjoining sacrificial layers to pattern a transistor control electrode in the second defined area; and
completing formation of transistors in both the first defined area and the second defined area.
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Abstract
A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area.
31 Citations
20 Claims
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1. A method comprising:
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providing a substrate having a first defined area and a second defined area that is electrically separated from first defined area; providing a first layer of gate material overlying the substrate in both the first defined area and the second defined area; providing multiple adjoining sacrificial layers overlying the first layer of gate material; using the multiple adjoining sacrificial layers to form transistor control electrodes in the first defined area wherein at least one of the adjoining sacrificial layers is not completely removed; using at least one of the adjoining sacrificial layers to pattern a transistor control electrode in the second defined area; and completing formation of transistors in both the first defined area and the second defined area. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of forming an integrated circuit comprising a first region and a second region formed over a substrate and separated by an isolation region, the method comprising:
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forming a first gate electrode material layer overlying the substrate in both the first region and the second region; forming a plurality of sacrificial layers overlying the first gate electrode material layer in both the first region and the second region prior to forming any devices in the first region and the second region; using the plurality of sacrificial layers to form a first type of device in the first region; and using at least one of the plurality of sacrificial layers to form a second type of device in the second region. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method of forming an integrated circuit comprising a memory region and a logic region formed over a substrate and separated by an isolation region, the method comprising:
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forming a first gate electrode material layer overlying the substrate in both the memory region and the logic region; forming a plurality of sacrificial layers overlying the first gate electrode material layer in both the memory region and the logic region prior to forming any devices in the memory region and the logic region; using the plurality of sacrificial layers to form a non-volatile memory device in the memory region; and using at least one of the plurality of sacrificial layers to form a logic device in the logic region, wherein the at least one of the plurality of sacrificial layers used to form the logic device is an anti-reflective coating (ARC) layer used to pattern a gate electrode corresponding to the logic region. - View Dependent Claims (17, 18, 19, 20)
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Specification