WAFER BONDING METHOD

• US 20090111241A1
• Filed: 12/29/2008
• Published: 04/30/2009
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Granted Patent: US 7,632,738 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29199 Material of the matrix
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 Fillers
• CPC Class Codes: H01L 2224/29299 Base material
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A method includes steps of providing first and second substrates, and forming a bonding interface between them using a conductive bonding region. A portion of the second substrate is removed to form a mesa structure. A vertically oriented semiconductor device is formed with the mesa structure. A portion of the conductive bonding region is removed to form a contact. The vertically oriented semiconductor device is carried by the contact.

Claims

1. A method, comprising:

providing first and second substrates;

forming a bonding interface between the first and second substrates with a conductive bonding region; and

removing a portion of the second substrate;

wherein the second substrate includes a stack of semiconductor material layers.

2. The method of claim 1, wherein the portion of the second substrate is removed after the bonding interface is formed.

3. The method of claim 1, further including forming a vertically oriented semiconductor device.

4. The method of claim 1, further including removing a portion of the conductive bonding region.

5. The method of claim 1, wherein the step of removing the portion of the second substrate includes forming a mesa structure.

6. The method of claim 5, further including removing a portion of the conductive bonding region.

7. The method of claim 5, further including removing a portion of the conductive bonding region so the mesa structure is carried by a contact.

8. The method of claim 5, further including forming a vertically oriented semiconductor device with the mesa structure.

9. A method, comprising:

providing first and second substrates;

using a conductive bonding region to form a bonding interface between the first and second substrates; and

forming a vertically oriented semiconductor device.

10. The method of claim 9, further including heating the conductive bonding region to reduce its number of defects.

11. The method of claim 9, further including removing a portion of the conductive bonding region after the bonding interface is formed.

12. The method of claim 9, wherein the vertically oriented semiconductor device is formed after the bonding interface is formed.

13. The method of claim 9, wherein the step of forming the vertically oriented semiconductor device includes forming a mesa structure.

14. The method of claim 13, further including removing a portion of the conductive bonding region so the mesa structure is carried by a contact.

15. The method of claim 14, wherein the first substrate includes electrical circuitry connected to the vertically oriented semiconductor device through the bonding interface.

16. A method, comprising:

providing an interconnect region;

providing a substrate which includes a stack of semiconductor material layers;

forming a bonding interface between the interconnect region and substrate using a conductive bonding region; and

processing the substrate to form a mesa structure.

17. The method of claim 16, further including removing a portion of the conductive bonding region.

18. The method of claim 16, wherein the mesa structure includes a portion of the stack of semiconductor material layers.

19. The method of claim 16, further including forming a vertically oriented semiconductor device which includes a portion of the stack of semiconductor material layers.

20. The method of claim 16, wherein the interconnect region includes a conductive line connected to the mesa structure through the bonding interface.