METHOD FOR FABRICATING TRANSISTOR IN SEMICONDUCTOR DEVICE

• US 20090111255A1
• Filed: 10/28/2008
• Published: 04/30/2009
• Est. Priority Date: 10/29/2007
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Seo, Hye Jin, Kim, Su Ho, Lee, An Bae, Eun, Yong Seok
• Granted Patent: US 7,851,298 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.

Claims

1. A method for fabricating a transistor in a semiconductor device, comprising:

forming an etch stop layer pattern over a semiconductor substrate;

forming a semiconductor layer covering the etch stop layer pattern;

etching the semiconductor layer to form a recess trench that exposes an upper surface of the etch stop layer pattern;

removing the etch stop layer pattern exposed in the recess trench; and

forming a gate that fills the recess trench.

2. The method of claim 1, wherein forming the etch stop layer pattern comprises:

forming an etch stop layer having an etch selectivity to the semiconductor layer over the semiconductor substrate;

forming a photoresist pattern that exposes a portion of the etch stop layer overlapped with the recess trench; and

selectively etching the portion of the etch stop layer exposed by the photoresist pattern.

3. The method of claim 1, wherein forming the recess trench comprises:

forming a first mask layer pattern that exposes a portion of the semiconductor layer overlapped with a portion of the etch stop layer pattern over the semiconductor layer;

selectively etching the portion of the semiconductor layer exposed by the first mask layer pattern to expose the upper surface of the etch stop layer pattern.

4. The method of claim 1, comprising forming the etch stop layer pattern of a nitride layer.

5. The method of claim 4, comprising forming the nitride layer to a thickness in a range of 30 to 300 Å

.

6. The method of claim 4, wherein removing the etch stop layer pattern comprises etching the nitride layer using phosphoric acid.

7. The method of claim 1, comprising forming the etch stop layer pattern of a Phosphorous Silicate Glass (PSG) layer or a Boron Phosphorous Silicate Glass (BPSG) layer.

8. The method of claim 1, wherein forming the semiconductor layer comprises performing Chemical Vapor Deposition (CVD) on a silicon layer or epitaxially growing a silicon layer.

9. A method for fabricating a transistor in a semiconductor device, comprising:

forming an etch stop layer pattern over a semiconductor substrate;

forming a burying insulation layer over the etch stop layer pattern;

selectively etching the burying insulation layer to form an opening that exposes the etch stop layer pattern and a neighboring portion of the semiconductor substrate;

forming a semiconductor layer that fills the opening;

selectively etching the semiconductor layer to form a recess trench that exposes an upper surface of the etch stop layer pattern;

removing the etch stop layer pattern exposed in the recess trench; and

forming a gate that fills the recess trench.

10. The method of claim 9, further comprising:

,

forming a mask layer pattern for opening an active region so that a portion of the semiconductor substrate is exposed and set to the active region; and

forming an isolation trench by selectively etching the portion of the semiconductor substrate exposed by the mask layer pattern before forming the burying insulation layer,

wherein the burying insulation layer is formed so as to fill the isolation trench.

11. The method of claim 10, wherein the opening is overlapped with the active region, or is formed so as to open a region within the active region.

12. The method of claim 9, wherein forming the semiconductor layer comprises:

performing chemical vapor deposition on a silicon layer or epitaxially growing a silicon layer so as to fill the opening; and

planarizing the silicon layer to expose the upper surface of the burying insulation layer.

13. A method for fabricating a transistor in a semiconductor device, comprising:

forming an etch stop layer pattern over a semiconductor substrate;

forming a semiconductor layer over the semiconductor substrate so as to cover the etch stop layer pattern;

sequentially etching a portion of the semiconductor layer and a portion of the semiconductor substrate therebelow to form an isolation trench;

forming a burying insulation layer that fills the isolation trench;

selectively etching a remaining portion the semiconductor layer disposed over the etch stop layer pattern and exposed by the burying insulation layer to form a recess trench that exposes an upper surface of the etch stop layer pattern;

removing the etch stop layer pattern exposed in the recess trench; and

forming a gate that fills the recess trench.

14. The method of claim 13, wherein forming the isolation trench comprises:

forming a mask layer pattern for opening an active region so that some of the semiconductor layer and the semiconductor substrate are set to the active region; and

selectively etching the portion of the semiconductor layer exposed by the mask layer pattern and selectively etching the portion of the semiconductor substrate therebelow to form the isolation trench.