EQUIVALENT GATE COUNT YIELD ESTIMATION FOR INTEGRATED CIRCUIT DEVICES

• US 20090112352A1
• Filed: 01/05/2009
• Published: 04/30/2009
• Est. Priority Date: 05/12/2006
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Barnett, Thomas S., Weger, Alan J., Lee, Gie, Jaji, Sebnem, Bickford, Jeanne P., Trapp, Brian M., Kravec, Kerry A., Lai, Wing L., Chang, William Y., Chatty, Rashmi D.
• Application Number:
  US12/348,549
• Publication Number:
  US 20090112352A1
• Time in Patent Office: Days
• US Class Current: 700/121
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A storage medium including a method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

Claims

1. A storage medium, comprising:

a computer readable computer program code including instructions that, when executed by a computer, implement a method of modeling yield for semiconductor products, wherein the method comprises;

determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements;

assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products, and thereafter updating the expected number of faults for each library element in response to observed yield;

establishing a database, the database including the die size and expected faults for each of the library elements;

estimating integrated circuit product die size;

selecting library elements to be used to create the integrated circuit die;

obtaining fault and size data for each of the selected library elements;

summing the adjusted estimated faults for each of the library elements; and

calculating estimated yield;

wherein the expected total number of faults for an integrated circuit die having N different library element types is determined by the expression;

$\mathrm{\lambda <br><br>}<br><br>\left(t\right)=\underset{i=1}{\overset{N}{\sum <br><br>}}<br><br>n_i<br><br>r_i<br><br>{\mathrm{\lambda <br><br>}}_i<br><br>{\mathrm{\tau <br><br>}}_i<br><br>F<br><br>\left(t\right);<br><br>$

wherein

t=time for which yield estimate is needed;

λ

(t)=total number of faults per chip at time t;

n_i total number of library elements of type i present on the integrated circuit die;

r_i redundancy factor for library element i;

λ

_i=estimated number of faults for the i^th library element;

τ

_i=adjustment factor for the i^th library element, determined by comparing the yield data for that library element with the estimated value λ

_i; and

F(t)=learning factor at time t.

2. The storage medium of claim 1, wherein updating the expected faults for each library element in response to observed yield further comprises:

identifying yield loss associated with individual library elements;

modifying faults for the library element in the database; and

using revised fault entry for subsequent product yield estimates.

3. A storage medium, comprising:

a computer readable computer program code including instructions that, when executed by a computer, implement a method of modeling yield for semiconductor products, wherein the method comprises;

determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements;

assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products, and thereafter updating the expected number of faults for each library element in response to observed yield;

establishing a database, the database including the die size and expected faults for each of the library elements;

estimating integrated circuit product die size;

selecting library elements to be used to create the integrated circuit die;

obtaining fault and size data for each of the selected library elements;

summing the adjusted estimated faults for each of the library elements; and

calculating estimated yield, wherein the calculated yield is determined by the expression;

$Y<br><br>\left(t\right)=Y_C<br><br>\left(t\right)·<br><br>Y_{0<br><br>i}<br><br>\left(t\right)<br><br>\frac{1}{{\left(1+\mathrm{\lambda <br><br>}<br><br>\left(t\right)/a_i\right)}^{a_i}};<br><br>$

wherein

Y(t)=wafer test yield for the integrated circuit die;

Y_0i(t)=gross systematic test yield for technology i;

Y_C(t)=chip custom circuit-limited yield (CLY) factor;

λ

(t)=total average number of faults per chip; and

a_i=cluster factor.

4. The storage medium of claim 3, wherein the wafer test yield for each library element is determined by accessing equivalent gate count information for each library element, the predicted fault information stored in a database.