BATTERY PACK, METHOD OF CHARGING SECONDARY BATTERY AND BATTERY CHARGER

• US 20090112496A1
• Filed: 10/29/2008
• Published: 04/30/2009
• Est. Priority Date: 10/30/2007
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Isao
• Granted Patent: US 9,172,261 B2
• Time in Patent Office: Days
• US Class Current: 702/63
• CPC Class Codes: H02J 7/0013 acting upon several batteries simultaneously or sequentially H02J7/1423 takes precedence
• CPC Class Codes: H02J 7/00302 Overcharge protection
• CPC Class Codes: H02J 7/00306 Overdischarge protection

Abstract

A battery pack includes a secondary battery including a plurality of cell blocks, a measuring section, a charge and discharge control switch, a protection circuit, and a memory. The measuring section detects a voltage, a current, and an internal resistance, of the secondary battery. The controller monitors the voltage and the current of the secondary battery and outputs a request signal indicative of a charge condition to charge the secondary battery in accordance with the charge condition which is set. The protection circuit monitors voltages of the plurality of cell blocks. The memory registers an initial internal resistance of the secondary battery. The controller calculates a deterioration coefficient by a ratio of the internal resistance detected by the measuring section to the initial internal resistance registered in the memory, and changes the charge condition in accordance with the deterioration coefficient.

Claims

1. A battery pack comprising:

a secondary battery including a plurality of cell blocks;

a measuring section configured to detect a voltage, a current, and an internal resistance, of the secondary battery;

a controller configured to monitor the voltage and the current of the secondary battery and output a request signal indicative of a charge condition to charge the secondary battery in accordance with the charge condition which is set;

a charge and discharge control switch configured to prevent overcharge and overdischarge;

a protection circuit configured to monitor voltages of the plurality of cell blocks; and

a memory which registers an initial internal resistance of the secondary battery,

wherein the controller calculates a deterioration coefficient by a ratio of the internal resistance detected by the measuring section to the initial internal resistance registered in the memory, and changes the charge condition in accordance with the deterioration coefficient.

2. The battery pack according to claim 1, wherein:

the charge condition includes a charging current value in constant-current charge, and

the charging current value is changed depending upon the deterioration coefficient.

3. The battery pack according to claim 1, wherein:

the charge condition includes a charging voltage value, and

the charging voltage value is changed depending upon the deterioration coefficient.

4. The battery pack according to claim 1, wherein the initial internal resistance is measured within a predetermined time period after manufacturing.

5. The battery pack according to claim 1, wherein:

the charge and discharge control switch is composed of a charge control FET and a discharge control FET, and

in a normal charge and discharge operation,

a control signal is set at a low level to turn the charge control FET and the discharge control FET on-state.

6. The battery pack according to claim 5, wherein:

when a battery voltage becomes an overcharge detection voltage, the charge and charge control switch is controlled to turn the charge control FET off so that a charging current does not flow, and

when the battery voltage becomes an overdischarge detection voltage, the charge and discharge control switch is controlled to turn the charge control FET off so that a charging current does not flow.

7. The battery pack according to claim 1, wherein:

when a cell voltage of the cell blocks exceeds a charge inhibiting voltage, the protection circuit melts a fuse connected to the protection circuit to become a permanent failure mode.

8. The battery pack according to claim 1, wherein:

the memory is included in a CPU, and

the CPU measures a magnitude and a direction of a current by using a current detection resister, and captures a battery temperature measured by a temperature detection element.

9. The battery pack according to claim 1, wherein the controller calculates the deterioration coefficient by a ratio of a maximum internal resistance among the plurality of cell blocks to the initial internal resistance of a cell block exhibiting the maximum internal resistance.

10. A method of charging a secondary battery, comprising:

detecting a voltage, a current, and an internal resistance, of a secondary battery; and

monitoring the voltage and the current of the secondary battery and outputting a request signal indicative of a charge condition to charge the secondary battery in accordance with the charge condition which is set,

wherein, in the step of outputting the request signal,

a deterioration coefficient is calculated by a ratio of the internal resistance detected to the initial internal resistance of the secondary battery registered in a memory, and the charge condition is changed depending upon the deterioration coefficient.

11. The method of charging a secondary battery according to claim 10, wherein:

the charge condition includes a charging current value in constant-current charge, and

the charging current value is changed depending upon the deterioration coefficient.

12. The method of charging a secondary battery according to claim 10, wherein:

the charge condition includes a charging voltage value, and

the charging voltage value is changed depending upon the deterioration coefficient.

13. The method of charging a secondary battery according to claim 10, wherein the initial internal resistance is measured within a predetermined time period after manufacturing.

14. The method of charging a secondary battery according to claim 10, wherein:

the secondary battery includes a plurality of cell blocks, and

the controller calculates the deterioration coefficient by a ratio of a maximum internal resistance among the plurality of cell blocks to the initial internal resistance of a cell block exhibiting the maximum internal resistance.

15. A battery charger comprising:

a secondary battery;

a measuring section configured to detect a voltage, a current, and an internal resistance, of the secondary battery;

a controller configured to monitor the voltage and the current of the secondary battery and output a request signal indicative of a charge condition to charge the secondary battery in accordance with the charge condition which is set;

a memory which registers an initial internal resistance of the secondary battery; and

a charge controller configured to control outputs of the charging current and the charging voltage of the secondary battery in accordance with the request signal outputted from the controller,

wherein the controller calculates a deterioration coefficient by a ratio of the internal resistance detected by the measuring section to the initial internal resistance registered in the memory, and changes the charge condition depending upon the deterioration coefficient.

16. The battery charger according to claim 15, wherein:

the charge condition includes a charging current value in constant-current charge, and

the charging current value is changed depending upon the deterioration coefficient.

17. The battery charger according to claim 15, wherein:

the charge condition includes a charging voltage value, and

the charging voltage value is changed depending upon the deterioration coefficient.

18. The battery charger according to claim 15, wherein the initial internal resistance is measured within a predetermined time period after manufacturing.

19. The battery charger according to claim 15, wherein:

the secondary battery includes a plurality of cell blocks, and

the controller calculates the deterioration coefficient by a ratio of a maximum internal resistance among the plurality of cell blocks to the initial internal resistance of a cell block exhibiting the maximum internal resistance.