BUS TERMINATOR/MONITOR/BRIDGE SYSTEMS AND METHODS

• US 20090113108A1
• Filed: 10/31/2007
• Published: 04/30/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: DuBois, Mark D., Becker, Karl H., Dodgen, David R.
• Granted Patent: US 7,661,024 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

Computing systems including first and second processors configured to control first and second buses, respectively, and a terminator-monitor-bridge (TMB) device coupled between the first and second buses are provided. The TMB device is configured to selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively. TMB devices and methods for operating the TMB devices in accordance with the above configuration are also provided.

Claims

1. A computing system, comprising:

a first bus;

a second bus;

a first processor coupled to and configured to control the first bus;

a second processor coupled to and configured to control the second bus; and

a terminator-monitor-bridge (TMB) device coupled between the first bus and the second bus, the TMB device configured to selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively.

2. The computing system of claim 1, further comprising:

a first plurality of devices in communication with the first processor via the first bus; and

a second plurality of devices in communication with the second processor via the second bus, wherein the TMB device is configured to;

enable the first processor to control at least a portion of the second plurality of devices if a fault is detected on the second bus, and

enable the second processor to control at least a portion of the first plurality of devices if a fault is detected on the first bus.

3. The computing system of claim 1, wherein the TMB is configured to:

temporarily enable the first processor to control the portion of the second bus if the fault is detected on the second bus; and

temporarily enable the second processor to control the portion of the first bus if the fault is detected on the first bus.

4. The computing system of claim 3, wherein the TMB is further configured to:

temporarily disable the first processor from controlling the portion of the first bus if the fault is detected on the first bus; and

temporarily disable the second processor from controlling the portion of the second bus if the fault is detected on the second bus.

5. The computing system of claim 4, wherein the TMB is further configured to:

enable the first processor to re-control the portion of the first bus if the fault on the first bus is a first non-processor fault; and

enable the second processor to re-control the portion of the second bus if the fault on the second bus is a second non-processor fault.

6. The computing system of claim 1, further comprising:

a first computing device including the first processor; and

a second computing device including the second processor.

7. The computing system of claim 1, wherein the first bus is a universal bus (USB) and the second bus is a USB.

8. The computing system of claim 1, wherein the first bus is an IEEE 1394 bus and the second bus is an IEEE 1394 bus.

9. The computing system of claim 1, wherein the first bus is an RS 422 bus and the second bus is an RS 422 bus.

10. The computing system of claim 1, wherein the first bus is an Ethernet bus and the second bus is an Ethernet bus.

11. A method for operating a terminator-monitor-bridge (TMB) device coupled between a first bus controlled by a first processor and a second bus controlled by a second processor, the method comprising the steps of:

monitoring the first bus and the second bus for faults;

at least temporarily enabling the first processor to control a portion of the second bus if a fault is detected on the second bus; and

at least temporarily enabling the second processor to control a portion of the first bus if a fault is detected on the first bus.

12. The method of claim 11, further comprising the steps of:

enabling, on a non-temporary basis, the first processor to control the portion of the second bus if the fault on the second bus is related to the second processor; and

enabling, on a non-temporary basis, the second processor to control the portion of the first bus if the fault on the first bus is related to the second processor.

13. The method of claim 11, further comprising the steps of:

at least temporarily disabling the first processor from controlling the portion of the first bus if the fault on the first bus is detected; and

at least temporarily disabling the second processor from controlling the portion of the second bus if the fault on the second bus is detected.

14. The method of claim 13, further comprising the steps of:

enabling the first processor to re-control the portion of the first bus if the fault on the first bus is a first non-processor fault; and

enabling the second processor to re-control the portion of the second bus if the fault on the second bus is a second non-processor fault.

15. The method of claim 11, further comprising the steps of:

reporting bus status information including the fault for the second bus on the first bus; and

reporting bus status information including the fault for the first bus on the second bus.

16. The method of claim 11, wherein the step of at least temporarily enabling the first processor to control the portion of the second bus comprises the step of enabling the first processor to control the portion of the second bus independent of input other than the fault detected on the second bus;

and

wherein the step of at least temporarily enabling the second processor to control the portion of the first bus comprises the step of enabling the second processor to control the portion of the first bus independent of input other than the fault detected on the first bus.

17. A terminator-monitor-bridge (TMB) device configured to be coupled to a first bus controlled by a first processor and a second bus controlled by a second processor, the TMB device comprising:

means for monitoring the first bus and the second bus for faults;

means for at least temporarily enabling the first processor to control a portion of the second bus if a fault is detected on the second bus; and

means for at least temporarily enabling the second processor to control a portion of the first bus if a fault is detected on the first bus.

18. The TMB device of claim 17, further comprising:

means for enabling, on a non-temporary basis, the first processor to control the portion of the second bus if the fault on the second bus is related to the second processor; and

means for enabling, on a non-temporary basis, the second processor to control the portion of the first bus if the fault on the first bus is related to the second processor.

19. The TMB device of claim 17, further comprising:

means for at least temporarily disabling the first processor from controlling the portion of the first bus if the fault on the first bus is detected; and

means for at least temporarily disabling the second processor from controlling the portion of the second bus if the fault on the second bus is detected.

20. The TMB device of claim 19, further comprising:

means for enabling the first processor to re-control the portion of the first bus if the fault on the first bus is a first non-processor fault; and

means for enabling the second processor to re-control the portion of the second bus if the fault on the second bus is a second non-processor fault.