Data processing with time-based memory access
First Claim
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1. A method of providing a data processor with access to a plurality of memory locations in a memory, comprising:
- independently of the data processor, accessing the memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses; and
making said continually repeating sequence of memory location accesses available to the data processor.
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Abstract
Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available for access.
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Citations
45 Claims
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1. A method of providing a data processor with access to a plurality of memory locations in a memory, comprising:
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independently of the data processor, accessing the memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses; and making said continually repeating sequence of memory location accesses available to the data processor. - View Dependent Claims (2)
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3. A method of providing a plurality of data processors with shared access to a memory having a plurality of memory locations, comprising:
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independently of the data processors, accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses; making said first continually repeating sequence of memory location accesses available to a first one of the data processors; independently of the data processors, accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses; and making said second continually repeating sequence of memory location accesses available to a second one of the data processors. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory apparatus for use with a data processor, comprising:
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a memory having a plurality of memory locations; a memory controller coupled to said memory and cooperable therewith independently of the data processor for accessing said memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses; and a bus coupled to said memory and adapted for coupling to the data processor to make said continually repeating sequence of memory location accesses available to the data processor. - View Dependent Claims (15, 16, 17, 18)
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19. A memory apparatus for use with a plurality of data processors, comprising:
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a memory having a plurality of memory locations; a memory controller coupled to said memory and cooperable therewith independently of the data processors for accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses, and accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses; a first bus coupled to said memory and adapted for coupling to a first one of the data processors to make said first continually repeating sequence of memory location accesses available to the first data processor; and a second bus coupled to said memory and adapted for coupling to a second one of the data processors to make said second continually repeating sequence of memory location accesses available to the second data processor. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A data processing apparatus, comprising:
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a data processor; a memory having a plurality of memory locations; a memory controller coupled to said memory and cooperable therewith independently of said data processor for accessing said memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses; and said memory coupled to said data processor to make said continually repeating sequence of memory location accesses available to said data processor.
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31. A data processing apparatus, comprising:
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first and second data processors; a memory having a plurality of memory locations; a memory controller coupled to said memory and cooperable therewith independently of said first and second data processors for accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses, and accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses; said memory coupled to said first and second data processors to make said first and second continually repeating sequences of memory location accesses respectively available to said first and second data processors.
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32. A data processing apparatus, comprising:
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a data processor; a memory having a plurality of memory locations; a memory controller coupled to said memory and cooperable therewith independently of said data processor for accessing said memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses; said memory coupled to said data processor to make said continually repeating sequence of memory location accesses available to said data processor; and a user interface coupled to said data processor to permit user access to said data processor.
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33. A data processing apparatus, comprising:
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first and second data processors; a memory having a plurality of memory locations; a memory controller coupled to said memory and cooperable therewith independently of said first and second data processors for accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses, and accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses; said memory coupled to said first and second data processors to make said first and second continually repeating sequences of memory location a accesses respectively available to said first and second data processors; and a user interface coupled to said first data processor to permit user access to said first data processor.
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34. A data processing apparatus, comprising:
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a data processing portion; and a memory interface portion coupled to said data processing portion, said memory interface portion configured to interface with a memory apparatus that provides access to a plurality of memory locations in a continually repeating sequence of memory location accesses, and to make said continually repeating sequence of memory location accesses available to said data processing portion. - View Dependent Claims (35, 36)
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37. A method of transferring first and second vectors from a memory apparatus to a data processing apparatus, wherein said first vector includes a first plurality of vector components respectively stored in a first plurality of memory locations in the memory apparatus, and wherein said second vector includes a second plurality of vector components respectively stored in a second plurality of memory locations in the memory apparatus, comprising:
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independently of the data processing apparatus, accessing the first plurality of memory locations sequentially to provide the first plurality of vector components in a first sequence; sequentially loading the first vector components of the first sequence into respective data processing elements of the data processing apparatus; independently of the data processing apparatus, accessing the second plurality of memory locations sequentially to provide the second plurality of vector components in a second sequence; and sequentially loading the second vector components of the second sequence respectively into said data processing elements of the data processing apparatus.
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38. A memory apparatus, comprising:
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a first memory unit including a first plurality of memory locations and a first memory controller coupled to said first plurality of memory locations, said first memory controller configured to produce access signaling associated with accesses of said first plurality of memory locations; and a second memory unit including a second plurality of memory locations and a second memory controller coupled to said second plurality of memory locations, said second memory controller configured to produce access signaling associated with accesses of said second plurality of memory locations, said second memory controller coupled to said first memory controller and configured to produce access signaling associated with an access of one of said second plurality of memory locations in response to access signaling produced by said first memory controller and associated with an access of one of said first plurality of memory locations. - View Dependent Claims (39, 40)
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41. A DRAM apparatus, comprising:
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a plurality of DRAM cells; an access controller coupled to said DRAM cells and cooperable therewith for executing a DRAM access operation to access said DRAM cells; and a refresh controller coupled to said access controller and said DRAM cells for controlling refresh of said DRAM cells based on signaling that said access controller produces to implement said DRAM access operation.
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42. The apparatus of claim 41, wherein said DRAM access operation accesses said DRAM cells sequentially and repetitively to produce a continually repeating sequence of DRAM cell accesses.
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42-1. A method of controlling refresh of DRAM cells, comprising:
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executing a DRAM cell access operation that accesses the DRAM cells; and controlling refresh of the DRAM cells based on signaling that is used to implement said DRAM cell access operation.
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43. A data processing apparatus, comprising:
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a data processing portion that executes a data processing application; a memory interface portion coupled to said data processing portion to interface said data processing portion to a memory apparatus that provides access to a plurality of memory locations in a continually repeating sequence of memory location accesses that occur during respectively corresponding, periodically repeating memory location access intervals; and said data processing portion adapted to execute predetermined operations of said data processing application during predetermined ones of said memory location access intervals selected based on a characteristic of the information associated with said predetermined ones of said memory location access intervals. - View Dependent Claims (44)
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45. A data processing method, comprising:
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executing a data processing application; accessing a plurality of memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses that occur during respectively corresponding, periodically repeating memory location access intervals; and said executing including executing predetermined operations of said data processing application during predetermined ones of said memory location access intervals selected based on a characteristic of the information associated with said predetermined ones of said memory location access intervals.
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Specification