RECONFIGURABLE ARRAY PROCESSOR FOR FLOATING-POINT OPERATIONS
First Claim
Patent Images
1. A processor comprising:
- an array of processing elements arranged to enable a floating-point operation, wherein each processing element includes an arithmetic logic unit toreceive two input values, andperform integer arithmetic on the received input values; and
wherein the processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.
3 Assignments
0 Petitions
Accused Products
Abstract
A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.
-
Citations
47 Claims
-
1. A processor comprising:
-
an array of processing elements arranged to enable a floating-point operation, wherein each processing element includes an arithmetic logic unit to receive two input values, and perform integer arithmetic on the received input values; and wherein the processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A reconfigurable array processor comprising:
-
an array of processing elements configured to perform one or more floating-point operations, wherein the processing elements in the array are connected together in groups of two or more processing elements; a configuration cache connected to the array to store a context configured to control one or more arithmetic operations performed by the processing elements in each column or row of the PE array, and enable data communications among the processing element; and a frame buffer connected to the array that operates as a cache memory to store an interim result of the one or more arithmetic operations performed by the array. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
-
-
28. A computing platform comprising:
-
a reconfigurable array processor comprising a plurality of components including; an array of processing elements configured to perform one or more floating-point operations, wherein the processing elements in the array are connected together in groups of two or more processing elements; a configuration cache connected to the array to store a context configured to control one or more arithmetic operations performed by the processing elements in each column or row of the PE array, and enable data communications among the processing element; and a frame buffer connected to the array that operates as a cache memory to store an interim result of the one or more arithmetic operations performed by the array; a system bus connected to the reconfigurable array processor; and a control and memory unit connected to the reconfigurable array processor through the system bus to control the reconfigurable array processor and store data. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
-
-
42. A method of generating a reconfigurable array comprising:
-
generating one or more floating-point unit-processing elements by arranging processing elements of a processing element array, wherein generating the one or more floating-point unit-processing elements includes grouping together two or more processing elements; performing a pipeline operation by temporally mapping contexts stored in registers of a configuration cache to the generated one or more floating-point unit-processing elements; and generating a mesh structure by applying a connectivity structure to the processing element array. - View Dependent Claims (43, 44, 46, 47)
-
-
45. A method comprising:
-
receiving at least two operands, wherein each operand includes at least an exponent value, a sign value and a mantissa value; processing the operands comprising; when the processing includes multiplication or division operation, generating an output exponent by adding or subtracting the exponent values of the received operands, and generating an output mantissa by multiplying or dividing the mantissa values and sign values of the received operands; and detecting whether the generated output exponent and the output mantissa are final values or interim values for operating next floating-point unit-processing element.
-
Specification