RECONFIGURABLE ARRAY PROCESSOR FOR FLOATING-POINT OPERATIONS

• US 20090113169A1
• Filed: 05/23/2008
• Published: 04/30/2009
• Est. Priority Date: 09/11/2007
• Status: Active Grant

• Current Assignee: Pixelplus Co., Ltd.
• Original Assignee: Synergy Innovation Co., Ltd.
• Inventors: Jo, Man Hwee, Choi, Ki Young, Park, IL Hyun, Yang, Hoon Mo
• Granted Patent: US 8,078,835 B2
• Time in Patent Office: Days
• US Class Current: 712/15
• CPC Class Codes: G06F 2207/3824 Accepting both fixed-point and floating-point numbers
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence

Abstract

A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.

Claims

1. A processor comprising:

an array of processing elements arranged to enable a floating-point operation, wherein each processing element includes an arithmetic logic unit to

receive two input values, and

perform integer arithmetic on the received input values; and

wherein the processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.

2. The processor of claim 1, wherein the arithmetic logic unit comprises a 16-bit arithmetic logic unit, and the processing elements of the array are connected in a mesh structure to enable data communications among the connected processing elements.

3. The processor of claim 2, wherein the array is selectively configurable to perform at least one of:

an integer arithmetic operation using each processing element; and

a floating-point operation using each group of two or more processing elements connected together.

4. The processor of claim 3, wherein at least two processing elements in a row or a column of the array are connected together to form the two or more groups to perform floating-point operations.

5. The processor of claim 3, wherein the array is selectively configured to operate in an 8×

5 arrangement structure when performing the integer arithmetic operation, and operate in a 4×

5 arrangement structure in which the processing elements are connected in pairs in each column of the array when performing the floating-point operation.

6. The processor of claim 3, further comprising a configuration cache connected to the array to store a context that controls at least one of

the integer arithmetic and floating-point arithmetic operations performed by the processing elements in the columns or rows of the array, and

the data communications among the processing elements;

wherein the processing elements are configured in columns or rows based on the context to form a pipeline, and

forward a result of a pipeline operation to a direction designated by the context.

7. The processor of claim 6, wherein each of the two or more groups of two or more processing units is configured to

perform the integer arithmetic operation or the floating-point arithmetic operation through temporal mapping;

receive the context of a control signal so as to perform a multi-cycle operation; and

receive a next context after final values are through all cycles obtained.

8. The processor of claim 3, wherein the two or more groups of two or more processing elements are configured to perform four fundamental rules of arithmetic and transcendental function arithmetic for floating-point operations.

9. The processor of claim 8, wherein each of the two or more groups of two or more processing elements comprises two of the processing elements connected to perform the four fundamental rules of arithmetic, wherein the two connected processing elements in each group includes:

a mantissa processing element to receive signs and mantissas of two operands; and

an exponent processing element to receive exponents from the two operands.

10. The processor of claim 9, wherein

the mantissa processing element is connected to at least one of a multiplier and a divider to multiply or divide the mantissa of the two operands;

and

the exponent processing element is configured to add or subtract the exponents of the two operands.

11. The processor of claim 1, wherein each processing element comprises:

two multiplexers connected to the arithmetic logic unit to provide at least the two input values to the arithmetic logic unit;

a shifter connected to the arithmetic logic unit to perform a shift operation on a result received from the arithmetic logic unit;

a temporary register connected to the arithmetic logic unit and the shifter to store an interim result of the arithmetic logic unit and an interim result of the shifter; and

an output register connected to the arithmetic logic unit and the shifter to store a final result of the arithmetic logic unit and a final result of the shifter;

wherein each of the multiplexers is configured to select data from data received from a data bus, other processing elements and own register file, and input the selected data into the arithmetic logic unit, and

the final results stored in the output register are input into other processing elements or output through a data bus.

12. A reconfigurable array processor comprising:

an array of processing elements configured to perform one or more floating-point operations, wherein the processing elements in the array are connected together in groups of two or more processing elements;

a configuration cache connected to the array to store a context configured to

control one or more arithmetic operations performed by the processing elements in each column or row of the PE array, and

enable data communications among the processing element; and

a frame buffer connected to the array that operates as a cache memory to store an interim result of the one or more arithmetic operations performed by the array.

13. The reconfigurable array processor of claim 12, wherein

each of the processing elements comprises an arithmetic logic unit to receive and process two input values;

and

the processing elements of the array are connected in a mesh structure to enable data communications among the processing elements.

14. The reconfigurable array of processor of claim 13, wherein the array is selectively configured to:

perform an integer arithmetic operation using each of the processing elements;

or

perform the one or more floating-point operations using each of the two or more groups of two or more processing elements connected together.

15. The reconfigurable array processor of claim 14, wherein each of the two or more groups of two or more processing elements includes at least two processing elements in a row or a column of the array connected to perform the one or more floating-point operations.

16. The reconfigurable array processor of claim 15, wherein the array is selectively configured to operate in an 8×

5 arrangement structure when performing the integer arithmetic operation, and operate in a 4×

5 arrangement structure in which the processing elements are connected in pairs in each column of the array when performing the floating-point operation.

17. The reconfigurable array processor of claim 14, wherein the processing elements are configured in columns or rows based on the context to form a pipeline, and a result of a pipeline operation is forwarded to a direction designated by the context.

18. The reconfigurable processor of claim 17, wherein each of the two or more groups of two or more processing units is configured to

perform the integer arithmetic operation or the one or more floating-point arithmetic operations through temporal mapping;

receive the context of a control signal so as to perform a multi-cycle operation; and

receive a next context after final values through all cycles are obtained.

19. The reconfigurable array processor of claim 14, wherein the two or more groups of two or more processing elements are configured to perform four fundamental rules of arithmetic and transcendental function arithmetic for floating-point operations.

20. The reconfigurable array processor of claim 19, wherein each of the two or more groups of two or more processing elements comprises two of the processing elements connected to perform the four fundamental rules of arithmetic, wherein the two connected processing elements in each group includes:

a mantissa processing element to receive signs and mantissas of two operands; and

an exponent processing element to receive exponents from the two operands.

21. The reconfigurable processor of claim 20, wherein

the mantissa processing element is connected to at least one of a multiplier and a divider to multiply or divide the mantissa of the two operands;

and

the exponent processing element is configured to add or subtract the exponents of the two operands.

22. The reconfigurable array processor of claim 21, wherein the frame buffer has a 24-bit floating-point format.

23. The reconfigurable array processor of claim 22, wherein the 24-bit floating-point format includes one sign bit, eight exponent bits, and fifteen mantissa bits.

24. The reconfigurable array processor of claim 23, wherein

the mantissa processing element is configured to

convert the received signs and mantissas of the two operands into the one sign bit and the fifteen mantissa bits of the frame buffer, and

store the converted one sign bit and the fifteen mantissa bits in the frame buffer;

and

the exponent processing element is configured to

convert the received exponents of the two operands into the eight exponent bits of the frame buffer, and

store the converted eight exponent bits in the frame buffer.

25. The reconfigurable array processor of claim 14, wherein each processing element comprises:

two multiplexers connected to the arithmetic logic unit to provide at least the two input values to the arithmetic logic unit;

a shifter connected to the arithmetic logic unit to perform a shift operation on a result received from the arithmetic logic unit;

a temporary register connected to the arithmetic logic unit and the shifter to store an interim result of the arithmetic logic unit and an interim result of the shifter; and

an output register connected to the arithmetic logic unit and the shifter to store a final result of the arithmetic logic unit and a final result of the shifter;

wherein each of the multiplexers is configured to select data from data received from a data bus, other processing elements and own register file, and input the selected data into the arithmetic logic unit, and

the final results stored in the output register are input into other processing elements or output through a data bus.

26. The reconfigurable array processor of claim 12, wherein the array comprises a coarse-grained reconfigurable array.

27. The reconfigurable processor of claim 26, further comprising a reconfigurable array control unit connected to the array to control operations of the array, the configuration cache and the frame buffer.

28. A computing platform comprising:

a reconfigurable array processor comprising a plurality of components including;

an array of processing elements configured to perform one or more floating-point operations, wherein the processing elements in the array are connected together in groups of two or more processing elements;

a configuration cache connected to the array to store a context configured to

control one or more arithmetic operations performed by the processing elements in each column or row of the PE array, and

enable data communications among the processing element; and

a frame buffer connected to the array that operates as a cache memory to store an interim result of the one or more arithmetic operations performed by the array;

a system bus connected to the reconfigurable array processor; and

a control and memory unit connected to the reconfigurable array processor through the system bus to control the reconfigurable array processor and store data.

29. The computing platform of claim 28, wherein the control and memory unit comprises:

an embedded core processing and controlling data;

an external memory storing data; and

a direct memory access controller transferring data.

30. The computing platform of claim 29, wherein the embedded core comprises a reduced instruction set computer processor or a hybrid processor having both the characteristics of the reduced instruction set computer processor and a complex instruction set computer processor.

31. The computing platform of claim 30, wherein the computing platform is implemented in a system on chip structure to connect the components of the reconfigurable array processor to components of the control and memory unit through the system bus.

32. The computing platform of claim 28, wherein

each of the processing elements comprises an arithmetic logic unit to receive and process two input values;

and

the processing elements of the array are connected in a mesh structure to enable data communications among the processing elements.

33. The computing platform of claim 32, wherein the array is selectively configured to:

perform an integer arithmetic operation using each of the processing elements;

or

perform the one or more floating-point operations using each of the two or more groups of two or more processing elements connected together.

34. The computing platform of claim 33, wherein the processing elements are configured in columns or rows based on the context to form a pipeline, and a result of a pipeline operation is forwarded to a direction designated by the context.

35. The computing platform of claim 34, wherein each of the two or more groups of two or more processing units is configured to

perform the integer arithmetic operation or the one or more floating-point arithmetic operations through temporal mapping;

receive the context of a control signal so as to perform a multi-cycle operation; and

receive a next context after final values through all cycles are obtained.

36. The computing platform of claim 30, wherein the two or more groups of two or more processing elements are configured to perform four fundamental rules of arithmetic and transcendental function arithmetic for floating-point operations.

37. The computing platform of claim 36, wherein each of the two or more groups of two or more processing elements comprises two of the processing elements connected to perform the four fundamental rules of arithmetic, wherein the two connected processing elements in each group includes:

a mantissa processing element to receive signs and mantissas of two operands; and

an exponent processing element to receive exponents from the two operands.

38. The computing platform of claim 37, wherein

the mantissa processing element is connected to at least one of a multiplier and a divider to multiply or divide the mantissa of the two operands;

and

the exponent processing element is configured to add or subtract the exponents of the two operands.

39. The computing platform of claim 36, wherein the frame buffer has a 24-bit floating-point format including one sign bit, eight exponent bits, and fifteen mantissa bits.

40. The computing platform of claim 32, wherein each processing element comprises:

two multiplexers connected to the arithmetic logic unit to provide at least the two input values to the arithmetic logic unit;

a shifter connected to the arithmetic logic unit to perform a shift operation on a result received from the arithmetic logic unit;

a temporary register connected to the arithmetic logic unit and the shifter to store an interim result of the arithmetic logic unit and an interim result of the shifter; and

an output register connected to the arithmetic logic unit and the shifter to store a final result of the arithmetic logic unit and a final result of the shifter;

wherein each of the multiplexers is configured to select data from data received from a data bus, other processing elements and own register file, and input the selected data into the arithmetic logic unit, and

the final results stored in the output register are input into other processing elements or output through a data bus.

41. The computing platform of claim 28, wherein the reconfigurable array processor comprises a coarse-grained reconfigurable array, and the reconfigurable array processor comprises a reconfigurable array control unit connected to the array to control the components of the reconfigurable array processor.

42. A method of generating a reconfigurable array comprising:

generating one or more floating-point unit-processing elements by arranging processing elements of a processing element array, wherein generating the one or more floating-point unit-processing elements includes grouping together two or more processing elements;

performing a pipeline operation by temporally mapping contexts stored in registers of a configuration cache to the generated one or more floating-point unit-processing elements; and

generating a mesh structure by applying a connectivity structure to the processing element array.

43. The method of claim 42, wherein grouping together two or more processing elements comprises grouping together two or more processing elements in a row or column of the processing element array

44. The method of claim 42, wherein generating a mesh structure comprises connecting the generated floating-point unit-processing elements in a row and column.

46. The method of claim 43, comprising when detected that the generated output exponent and output mantissa are final values, storing the detected final values in a frame buffer.

47. The method of claim 43, comprising when detected that the generated output exponent and output mantissa are interim values, transferring the detected interim values to next floating-point unit-processing element in a row and/or column to perform the next operation.

45. A method comprising:

receiving at least two operands, wherein each operand includes at least an exponent value, a sign value and a mantissa value;

processing the operands comprising;

when the processing includes multiplication or division operation, generating an output exponent by adding or subtracting the exponent values of the received operands, and

generating an output mantissa by multiplying or dividing the mantissa values and sign values of the received operands; and

detecting whether the generated output exponent and the output mantissa are final values or interim values for operating next floating-point unit-processing element.