System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit

• US 20090113182A1
• Filed: 10/24/2007
• Published: 04/30/2009
• Est. Priority Date: 10/24/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Abernathy, Christopher M., Venton, Todd A., Burky, William E., Brown, Mary D.
• Application Number:
  US11/923,377
• Publication Number:
  US 20090113182A1
• Time in Patent Office: Days
• US Class Current: 712/216
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

A system and method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system. In response to a LSU determining that a load request from a load instruction missed a first level in a memory hierarchy, a LMQ allocates a load-miss queue entry corresponding to the load instruction. The LMQ associates at least one instruction dependent on the load request with the load-miss queue entry. Once data associated with the load request is retrieved, the LMQ selects at least one instruction dependent on the load request for execution on the next cycle. At least one instruction dependent on the load request is executed and a result is outputted.

Claims

1. A computer-implementable method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system, said computer-implementable method comprising:

determining if a load request from a load instruction missed a first level in a memory hierarchy;

in response to determining said load request missed a first level in a memory hierarchy, allocating a load-miss queue entry corresponding to said load instruction;

determining if at least one dispatched instruction dependent on said load request is located in at least one issue queue in said processing unit;

in response to determining at least one dispatched instruction dependent on said load request is located in at least one issue queue in said processing unit, associating said load-miss queue entry with said at least one dispatch instruction;

retrieving data associated with said load request into said first level in said memory hierarchy from another level within said memory hierarchy;

in response to said retrieving data associated with said load request, selecting said at least one dispatched instruction dependent on said load request for issue from said issue queue; and

in response to said selecting, issuing said dispatched instruction dependent on said load request on a next processing unit cycle;

executing said dispatched instruction in an execution unit; and

outputting a result of said executing.

2. The computer-implementable method according to claim 1, wherein said associating further comprises:

setting, within said load-miss queue entry, a dependent instruction identifier field and a valid identifier field, wherein said dependent identifier field associates said at least one dispatched instruction dependent on said load request with said load request, and wherein said valid identifier field indicates whether said at least one dispatched instruction dependent on said load request is valid.

3. The computer-implementable method according to claim 1, further comprising:

in response to determining said at least one dispatched instruction dependent on said load request is not a valid instruction, clearing said valid identifier field.

4. A system for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system, said system comprising:

at least one processing unit;

an interconnect coupled to said at least one processing unit; and

a computer usable medium embodying computer program code, said computer usable medium being coupled to said interconnect, said computer program code comprising instructions executable by said plurality of processors and configured for;

determining if a load request from a load instruction missed a first level in a memory hierarchy;

in response to determining said load request missed a first level in a memory hierarchy, allocating a load-miss queue entry corresponding to said load instruction;

determining if at least one dispatched instruction dependent on said load request is located in at least one issue queue in said processing unit;

in response to determining at least one dispatched instruction dependent on said load request is located in at least one issue queue in said processing unit, associating said load-miss queue entry with said at least one dispatch instruction;

retrieving data associated with said load request into said first level in said memory hierarchy from another level within said memory hierarchy;

in response to said retrieving data associated with said load request, selecting said at least one dispatched instruction dependent on said load request for issue from said issue queue; and

in response to said selecting, issuing said dispatched instruction dependent on said load request on a next processing unit cycle;

executing said dispatched instruction in an execution unit; and

outputting a result of said executing.

5. The system according to claim 4, wherein said instructions for associating are further configured for:

setting, within said load-miss queue entry, a dependent instruction identifier field and a valid identifier field, wherein said dependent identifier field associates said at least one dispatched instruction dependent on said load request with said load request, and wherein said valid identifier field indicates whether said at least one dispatched instruction dependent on said load request is valid.

6. The system according to claim 4, wherein said instructions are further configured for:

in response to determining said at least one dispatched instruction dependent on said load request is not a valid instruction, clearing said valid identifier field.