Method and systems for advanced reprogrammable boot codes and in-application programming of embedded microprocessor systems

• US 20090113196A1
• Filed: 10/27/2007
• Published: 04/30/2009
• Est. Priority Date: 10/27/2007
• Status: Active Grant

• Current Assignee: ASIX Electronics Corporation
• Original Assignee: ASIX Electronics Corporation
• Inventors: JAN, Hsun-Yao, Su, Ting-Han
• Granted Patent: US 7,886,141 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories

Abstract

This invention relates to an advanced system and method of reprogrammable boot codes and In Application Programming (IAP) of embedded systems by booting up with boot loader to shadow program codes on to an internal high speed SRAM and extending contiguously to external higher space memory for runtime applications, and supporting on-line IAP to update run-time firmware or boot loader driver through network communication by utilizing advanced address remapping scheme as well as supporting In System Programming (ISP) to program initial Flash memory via ISP adaptor.

Claims

1. An embedded system with efficient reconfigurable boot loader, comprising:

a processor;

a first memory medium coupled to said processor;

a second memory medium coupled to said processor; and

a boot loader coupled to said first memory medium, said second memory medium and said processor, wherein said boot loader is configured to copy an operation system codes from said first memory medium to said second memory medium during a second phase of a system reset cycle and said processor executes at least a portion of said operation system codes from said second memory medium after said second phase of said system reset cycle,

wherein said system reset cycle starts a first phase of a system reset cycle after said embedded system receiving a system reset signal,

wherein said boot loader generates a delayed reset signal to said processor during said second phase of a system reset cycle, and

wherein said first memory medium comprise non-volatile memory and said second memory medium comprises high speed internal Boot SRAM for Boot codes execution starting from lowest address of corresponding program memory space.

2. The embedded system in accordance with claim 1, wherein said operation system codes is stored in a memory space starting from lowest address of said first memory medium, and said copy an operation system codes further comprises copying to a corresponding program memory space starting from lowest address of said second memory medium during said second phase of said system reset cycle and said processor to execute at least a portion of said operation system codes from said corresponding memory space starting from lowest address of said second memory medium after said second phase of said system reset cycle.

3. The embedded system in accordance with claim 2, wherein said at least a portion of said operation system codes executed from said second memory medium by said processor includes a minimum set of self-sustained predefined operational tasks comprising at least one of system initiation, memory read/write access, input/output handling, application codes upgrading and network interface protocols.

4. The embedded system in accordance with claim 2, further comprises a multiplexing unit (MUX) coupled to said first memory medium, said processor and an in-system programming (ISP) controller, wherein said ISP controller is configured to reprogram said first memory medium through one or more dedicated ISP port or through a memory bus of said processor, wherein said MUX is configured to switch between the said ISP controller and said memory bus of said processor to select source to reprogram said first memory medium;

and a memory address remapping controller configured to remap a disabled memory address range to address range of said first memory medium in order to rewrite a new operation system codes into said first memory medium while said processor is executing said at least a portion of said operation system codes from said second memory medium.

5. The embedded system in accordance with claim 2, wherein said first phase of said system reset cycle comprises generating a first delayed reset signal to said boot loader in response to receiving said system reset signal.

6. The embedded system in accordance with claim 2, wherein a second phase of said reset cycle further comprises generating a second delayed reset signal to said processor in response to receiving said first delayed reset signal.

7. The embedded system in accordance with claim 2, wherein during said copying an operation system codes process, said internal Boot SRAM is in write-enable mode.

8. An embedded system with efficient reconfigurable in application programming comprising:

a processor;

a first memory medium coupled to said processor;

a second memory medium coupled to said processor; and

a boot loader coupled to said first memory medium, said second memory medium and said processor;

said boot loader is configured to copy an operation system codes from said first memory medium to said second memory medium during a system reset cycle and said processor executes at least a portion of said operation system codes from said second memory medium after said system reset cycle,

wherein said boot loader is configured to copy run-time application codes from a memory space starting from a higher address range of said first memory medium to a corresponding memory space starting from a higher address range of said second memory medium according to configuration within said at least a portion of said operation system codes, and said processor executes said run-time application codes from corresponding memory space starting from a higher address range of said second memory medium after completion of copying said run-time application codes from said higher address range of said first memory medium to said higher address range of said second memory medium;

a multiplexing unit (MUX) coupled to said first memory medium, said processor and an in-system programming (ISP) controller, wherein said ISP controller is configured to reprogram said first memory medium through one or more dedicated ISP port or through a memory bus of said processor, wherein said MUX is configured to switch between the said ISP controller and said memory bus of said processor to select source to reprogram said first memory medium,

wherein said first memory medium comprise non-volatile memory and said second memory medium comprises high speed internal Boot SRAM for Boot codes execution starting from lowest address of corresponding program memory space.

9. The embedded system in accordance with claim 8, wherein the first memory medium comprises non-volatile memory to store said operation system codes and a run-time application codes.

10. The embedded system in accordance with claim 8, wherein said at least a portion of said operation system codes executed from said second memory medium by said processor includes a minimum set of self-sustained predefined operational tasks comprising at least one of system initiation, memory read/write access, input/output handling, application codes upgrading and network interface protocols.

11. The embedded system in accordance with claim 10, said multiplexing unit further switches within two distinct modes:

an in-system programming mode and in-application programming mode.

12. The embedded system in accordance with claim 11, wherein during said in-system programming mode said multiplexing unit switches the programming source to said one or more dedicated ISP ports, and said in-system programming is executed via said one or more dedicated ISP ports independent of said processor operation modes.

13. The embedded system in accordance with claim 11, wherein during said in-application programming mode said multiplexing unit switches the programming source to said memory bus of said processor, and said in-application programming is executed while said processor executes said at least a portion of said operation system codes with said a minimum set of self-sustained operational tasks from said second memory medium.

14. The embedded system in accordance with claim 8, further comprises a memory address remapping controller configured to remap a disabled memory address range to address range of said first memory medium in order to rewrite a new operation system codes into said first memory medium while said processor is executing said at least a portion of said operation system codes from said second memory medium,

wherein said system reset cycle starts a first phase of a system reset cycle after said embedded system receiving a system reset signal.

15. An embedded system for efficient reconfigurable boot loader, comprising:

a processor;

a first memory medium coupled to said processor;

a second memory medium coupled to said processor;

a boot loader configured to copy an operation system codes from said first memory medium to said second memory medium during a system reset cycle and said processor executes at least a portion of said operation system codes by said processor from said second memory medium after a system reset cycle; and

a memory address remapping controller configured to remap a disabled memory address range to address range of said first memory medium in order to rewrite a new operation system codes into said first memory medium while said processor is executing said at least a portion of said operation system codes from said second memory medium,

wherein said first memory medium comprise non-volatile memory and said second memory medium comprises high speed internal Boot SRAM for Boot codes execution starting from lowest address of corresponding program memory space.

16. The embedded system in accordance with claim 15, wherein said at least a portion of said operation system codes executed from said second memory medium by said processor includes a minimum set of self-sustained predefined operational tasks comprising at least one of system initiation, memory read/write access, input/output handling, application codes upgrading and network interface protocols.

20. The embedded system in accordance with claim 15, further comprises a multiplexing unit (MUX) coupled to said first memory medium, said processor and an in-system programming (ISP) controller, wherein said ISP controller is configured to reprogram said first memory medium through one or more dedicated ISP port or through a memory bus of said processor, wherein said MUX is configured to switch between the said ISP controller and said memory bus of said processor to select source to reprogram said first memory medium,

wherein said system reset cycle starts a first phase of a system reset cycle after said embedded system receiving a system reset signal.

17. The embedded system in accordance with 16, wherein said memory address remapping controller further operates within two distinct modes:

a normal reconfiguration mode and an address-remapping reconfiguration mode.

18. The embedded system in accordance with claim 17, wherein during said normal reconfiguration mode said memory address remapping controller maps to same memory space of said first memory medium in a normal mode for rewriting run-time codes while said processor executes said at least a portion of said operation system codes from said second memory medium after a system reset cycle.

19. The embedded system in accordance with claim 17, wherein during said address-remapping reconfiguration mode said memory address remapping controller maps a disabled memory address range to the address range of said first memory medium in a memory address remapping mode for rewriting operation system boot codes while said processor executes said at least a portion of said operation system codes from said second memory medium after a system reset cycle.